Hi guys,
So, I've been poking and prodding FPGAs, and I just like to look at the synthesis/implementation results and the actual routing - it's aesthetically pleasing
When I was checking up on it I noticed a little block completely isolated from everything else. See attachement. Basically, two LUTs are connected from nowhere to nowhere... when I click on them to find out more it seems that they are a part of/related to a FIFO... most of which is somewhere else entirely. I can't find any mention of them in the constraints, DRC or anywhere - that said, I'm new to this kind of thing, so I may have overlooked something completely obvious.
Also, they are placed in the same area every time. I'm not sure if they are placed in the exact same spot, but it's possible.
This is not a problem - the device works well, but it's a bit of a mystery. Do you have any hints as to where to start looking for clues on why they are there? The device is an Artix 7 FPGA from Xilinx, the toolset is Vivado, newest version, the FIFO in question is a Xilinx IP block with two unrelated clocks.
Best regards,
David