I see some problems with the code also, but that should be in the report.
1.) check the resource usage ... is there anything used at all?
2.) coding style for VHDL
This code looks more like a testbench for me than any synthesizeable code.
"wait until rising_edge" even if its only used once in the process and it would be able to make this process sensitive to the clock "clk" its not an usual way to write VHDL code.
process should be written as:
p_process_name : process (clk, reset)
begin
if (reset = '0') then -- '0' or '1' depends if low or high active
.... reset all signals here
elsif clk'event and clk = '1' then -- this is for rising edge triggered process use "clk = '0'" for falling edge, might be usefull sometime but only special cases
... do your stuff here
end if;
end process p_process_name
The process name is not needed, but makes code better readable, after process the signals in brackets are the signalls where the process is sensitive on (your process is not sensitive to any signal)
variables ... sholdnt be used too much, you wont see them in simulation AND these are updated instant not like signals on the next clock edge, which confuses (specially beginners).
index ... count allways down and compare to zero, this uses much less resources (ok, for this not important, but using this many times on small devices and you might see what i mean)
LED(index) ... you count the index up to 15? but your LED array has only 6 entries
? this sould give a big warning. You dont know what this realy does in the end. Simulation might look good, but the implementation is sometimes totaly random, but with 6 i see a big problem and specially the values 7 will be random, the values 8 to 15 might repeat starting with 0. The index range is not reduced to the needed range.
I am not digging deeper as i would just rewrite the code and i am pretty sure that the problem is on the implementation, either the clock rate is a problem, but 50 MHz is not that much or altera does not like the coding style. (xilinx and altery use different synthesis programms for implementation).
First thing to check would be the pinout of the implementation, the "serial" output might not be shown at all.