New FPGAs from Renesas

[ataradov]

There are configuration bits and once SPI is disabled via OTP programming, it remains disabled.

But I also don't get overall idea you propose. Who would write the data into the flash and why you can't do the same directly and not involve FPGA at all?

[josuah]

My previous post was a bit unclear...

The idea was: since the OTP cannot be reprogrammed but will be there anyway, why not put a boot-loader in here. A bit like what FOMU and TinyFPGA did, but using the OTP storage for the bootloader instead...

Booting with "BOOT" button pressed:

Code: [Select]

                                 ┏━━━━bootloader━━━━ OTP storage (bootloader)
                                 v
USB port ───────X─────── FPGA (empty) ──────X─────── FLASH (empty)
                                 │
                                 X
                                 │
                            rest of the
                             hardware


Code: [Select]

                                 ┌─────────X──────── OTP storage (bootloader)
                                 │
USB port ━━━design━━━> FPGA (bootloader) ━━design━━> FLASH (design)
                                 │
                                 X
                                 │
                            rest of the
                             hardware

Booting with "BOOT" button released:

Code: [Select]

                                 ┌─────────X──────── OTP storage (bootloader)
                                 │
USB port ───────X─────── FPGA (empty) <━━━design━━━━ FLASH (design)
                                 │
                                 X
                                 │
                            rest of the
                             hardware


Code: [Select]

                                 ┌─────────X──────── OTP storage (bootloader)
                                 │
USB port ───────X─────── FPGA (design) ───────X───── FLASH (design)
                                 ^
                                 ┃
                                 v
                            rest of the
                             hardware

A bootloader is typically a piece of code that sits there there untouched for the entire life of the device, even across firmware upgrades, so I wondered if it would be a good fit for an OTP storage.

[ataradov]

Depending on how your USB is connected, it may be way easier to just connect the flash to the USB and program it directly. If it is a simple USB to UART, then your logic makes sense, but I don't think this will be supported (just guessing based on nothing really).

There is not enough logic capacity in that device that you would normally want it to be connected to the USB for applications. It is really a glue logic device.

[josuah]

Understood.
A traffic cop such as a tiny FPGA chip is no fit for a highway like USB.
Thank you for the feedback.

[Sal Ammoniac]

The IDE is very fast when synthesizing and generating a bitstream. Orders of magnitude faster than Vivado.

One thing I found curious in the synthesis log: 2. Executing SYNTH_XILINX pass.

[SiliconWizard]

Isn't it based on open source tools (or do I confuse this with some other vendor?) like Yosys?

[ataradov]

The IDE is very fast when synthesizing and generating a bitstream. Orders of magnitude faster than Vivado.

Have you seen the size of this device? It is trivial to synthesize that much.

[Sal Ammoniac]

The IDE is very fast when synthesizing and generating a bitstream. Orders of magnitude faster than Vivado.

Have you seen the size of this device? It is trivial to synthesize that much.

I tried synthesizing a tiny bit of Verilog -- about 16 lines... Took 46 seconds in Vivado, 1.5 seconds in this Renesas IDE.

[ataradov]

It is not about the size of the code, but about the size of the target device. No matter how small the design is, you need to process the whole device database in order to know how to fit your design into that device.

Plus those open tools do not even try to figure out constraints other than pin mapping (bare minimum for any tool).

[josuah]

Someone received the dev board from Mouser: https://hackaday.io/project/184088-goforge-a-renesas-fpga-board
See the comments:

I just receeived notice from Mouser that the SLG7DVKFORGE development board I ordered in April has shipped. The shipment is by UPS Ground, so I'll probably get it on Monday. David says he received his already and that it included the SLG47910V-SKT socket adapter and some sample chips. I already have two of the socket adapter and some sample chips, but presumably the DVK will include the newer version of the socket adapter. (Not that the differences are important.)

I still have two of the SLG47910C-SKT socket adapters (with samples) backordered for the 20-pad WCLSP part, but that's of much less interest.

The data sheets for the SLG47910 chip, the development board, the socket adapter, and (presumably) the low-cost evaluation board are still only available on request from Renesas. I've got the 2.1 data sheet and versions of the socket adapter manual for two different revisions of the socket adapter, but I have not yet been able to get the manual for the development board or the evaluation board. I have just emailed Renesas a request for this documentation, and an updated datasheet if there is one newer than revision 2.1 dated 3-Feb-2022.

A new release of the development software became available a few days ago. I use Fedora Linux, which isn't directly supported, so previously I'd installed their Ubuntu version into a virtual machine. With this new release, I tried runing their Debian dpkg through "alien" to convert it to an RPM. A little bit of elbow grease was required to avoid trivial directory ownership conflicts, but I was pleasantly surprised that the resulting RPM works fine on Fedora 36.

[scotcob]

I was getting really frustrated with the availability of the FPGA's and development kits from Renesas that I contacted them direct for status, basically they replied stating that middle of 2023 parts and kits will be available.

Full details as follows:
https://community.renesas.com/gpak-gfet/f/greenpak-greenfet/29049/forgefpga-availability

Hope this helps others on status of these devices.

[gnuarm]

That's bad news.  I was planning to use one of their parts.  If I can't get anything for six months, I can't design it in.

[DCW]

This is my first post to EEVblog.
Maybe someone else already mentioned this, but Renesas/Dialog didn't design the FPGA fabric in their ForgeFPGA -- it was licenced from Flex Logix:
https://semiengineering.com/micro-fpgas-and-embedded-fpgas/

[zapta]

What is the expected price of the SLG47910, e.g. compared to a SLG46826?

Not available yet, but I could find a preliminary PDF (below) and the latest GreenPAK tool release included fixes related to it so seems to be still alive.

[PCB.Wiz]

Looks like it competes with the iCE40, so the price has to be in that ball park.
It looks a bit slower, so maybe that means a bit cheaper too ?

[up8051]

What is the expected price of the SLG47910, e.g. compared to a SLG46826?

Not available yet, but I could find a preliminary PDF (below) and the latest GreenPAK tool release included fixes related to it so seems to be still alive.

Renesas has not been able to produce these chips over two years (12/2021, date of announcement of the chips).
They also cannot determine when they will be available. You can find information on the Renesas forum.
Until they are mass-available, it's just a waste of time.