Where to get the system reset signal on an ICE40UP5K ?

[zapta]

I am using the Upduino 3.1 ICE40UP5K-SG48ITR (PDF schematic below) with the open source tool chain (apio/yosys) and verilog. All the modules have a synchronous sys_reset input to initialize them on startup. Does the FPGA or tool chain already have a built in reset signal I can use?  If not, how should I about designing my own?

Currently I am using a simple timer that seems to work but would like to add a PLL and am not sure if I need to wait as well, so wonder if there is an out of the box solution or best practice.

Code: [Select]

`default_nettype none

module reset_gen (
    input sys_clk,
    output reg sys_reset
);

  // Relying on ICE40 behavior of reseting all DFF on power on reset.
  reg [3:0] counter = 0;

  always @(posedge sys_clk) begin
    if (counter < 10) begin
      sys_reset <= 1;
      counter   <= counter + 1;
    end else begin
      sys_reset <= 0;
    end
  end

endmodule