I'm confused about some simulation results, strobe confusion

[betocool]

Hey all,

I'm confused with the following situation. In a synchronous system where all signals are driven by the rising edge of a clock, the following statement:

Code: [Select]

if(rising_edge(clk)) then
           
            if (psram_state = PSRAM_RST) then
                delay <= delay + 1;
                if (delay = 35000) then
                    delay <= (others => '0');
                    psram_state <= PSRAM_IDLE;
                    read_i <= '1';
                    data_in <= ca(to_integer(ca_cnt));
                    ca_cnt <= ca_cnt + 1;
                end if;
            end if;

would set "read_i" and all other variables after "delay" has been detected to be 35000... for example



On the same simulation, in another module of the code, I wait for "read_i" to be set to '1' to kick off a process. But what I'm seeing is that the process gets kicked off on the rising edge of the clock as well as "read_i".

Code: [Select]

        if(rising_edge(clk_i)) then

            if (psram_state = PSRAM_IDLE) then
                if(read_i = '1') then
                    psram_state <= PSRAM_CMD;
                    wait_cnt <= X"00";
                    cmd_data <= data_in;
                end if;
            end if;
           --- Code goes on....



The main difference, the top part of the code runs in the testbench file, the second on a module that should be pure hardware. I am very very confused. That stuff used to trip me up a lot way back, and now I wonder what's happening or what I'm doing wrong.

Cheers,

Alberto

[Someone]

clk != clk_i

Zoom right in on the simulation (assuming it is a good simulator and will show the true delta cycles)

https://vhdlwhiz.com/delta-cycles-explained/

[betocool]

What a numpty! Yeah, ok, I didn't know that.

I was assigning

Code: [Select]

-- Clocks
clk_i <= clk;

in the testbench. I changed it to clk directly and it behaves as I expected it to.

Thanks man!

Cheers,

Alberto