The only changes I remember making were to remove the "NOT"s and then put them back in, but it did not work when I first put them back in.
Component
entity U_74150 is
Port ( E0 : in STD_LOGIC;
E1 : in STD_LOGIC;
E2 : in STD_LOGIC;
E3 : in STD_LOGIC;
E4 : in STD_LOGIC;
E5 : in STD_LOGIC;
E6 : in STD_LOGIC;
E7 : in STD_LOGIC;
E8 : in STD_LOGIC;
E9 : in STD_LOGIC;
E10 : in STD_LOGIC;
E11 : in STD_LOGIC;
E12 : in STD_LOGIC;
E13 : in STD_LOGIC;
E14 : in STD_LOGIC;
E15 : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR(4-1 downto 0);
W : out STD_LOGIC);
end U_74150;
architecture Behavioral of U_74150 is
begin
process (E0,E1,E2,E3,E4,E5,E6,E7,E8,E9,E10,E11,E12,E13,E14,E15,SEL)
begin
case SEL is
when "0000" => W <= NOT E0;
when "0001" => W <= NOT E1;
when "0010" => W <= NOT E2;
when "0011" => W <= NOT E3;
when "0100" => W <= NOT E4;
when "0101" => W <= NOT E5;
when "0110" => W <= NOT E6;
when "0111" => W <= NOT E7;
when "1000" => W <= NOT E8;
when "1001" => W <= NOT E9;
when "1010" => W <= NOT E10;
when "1011" => W <= NOT E11;
when "1100" => W <= NOT E12;
when "1101" => W <= NOT E13;
when "1110" => W <= NOT E14;
when "1111" => W <= NOT E15;
when others => W <= NOT '0';
end case;
end process;
end Behavioral;
and test bench
ENTITY U_74150_tb IS
END U_74150_tb;
ARCHITECTURE behavior OF U_74150_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT U_74150
PORT(
E0 : IN std_logic;
E1 : IN std_logic;
E2 : IN std_logic;
E3 : IN std_logic;
E4 : IN std_logic;
E5 : IN std_logic;
E6 : IN std_logic;
E7 : IN std_logic;
E8 : IN std_logic;
E9 : IN std_logic;
E10 : IN std_logic;
E11 : IN std_logic;
E12 : IN std_logic;
E13 : IN std_logic;
E14 : IN std_logic;
E15 : IN std_logic;
SEL : IN std_logic_vector(3 downto 0);
W : OUT std_logic
);
END COMPONENT;
--Inputs
signal E0 : std_logic := '0';
signal E1 : std_logic := '0';
signal E2 : std_logic := '0';
signal E3 : std_logic := '0';
signal E4 : std_logic := '0';
signal E5 : std_logic := '0';
signal E6 : std_logic := '0';
signal E7 : std_logic := '0';
signal E8 : std_logic := '0';
signal E9 : std_logic := '0';
signal E10 : std_logic := '0';
signal E11 : std_logic := '0';
signal E12 : std_logic := '0';
signal E13 : std_logic := '0';
signal E14 : std_logic := '0';
signal E15 : std_logic := '0';
signal SEL : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal W : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: U_74150 PORT MAP (
E0 => E0,
E1 => E1,
E2 => E2,
E3 => E3,
E4 => E4,
E5 => E5,
E6 => E6,
E7 => E7,
E8 => E8,
E9 => E9,
E10 => E10,
E11 => E11,
E12 => E12,
E13 => E13,
E14 => E14,
E15 => E15,
SEL => SEL,
W => W
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
E0 <= '1';
E1 <= '1';
E2 <= '1';
E3 <= '1';
E4 <= '1';
E5 <= '0';
E6 <= '1';
E7 <= '1';
E8 <= '1';
E9 <= '1';
E10 <= '1';
E11 <= '0';
E12 <= '0';
E13 <= '0';
E14 <= '0';
E15 <= '0';
SEL <= "0000";
wait for 10 ns;
SEL <= "0001";
wait for 10 ns;
SEL <= "0010";
wait for 10 ns;
SEL <= "0011";
wait for 10 ns;
SEL <= "0100";
wait for 10 ns;
SEL <= "0101";
wait for 10 ns;
SEL <= "0110";
wait for 10 ns;
SEL <= "0111";
wait for 10 ns;
SEL <= "1000";
wait for 10 ns;
SEL <= "1001";
wait for 10 ns;
SEL <= "1010";
wait for 10 ns;
SEL <= "1011";
wait for 10 ns;
SEL <= "1100";
wait for 10 ns;
SEL <= "1101";
wait for 10 ns;
SEL <= "1110";
wait for 10 ns;
SEL <= "1111";
wait for 10 ns;
SEL <= "0000";
wait;
end process;
END;
The test bench never changed. It is not hierarchical at this point because I wanted to get the first component working before I moved on.
@SiliconWizard what synthesis reports are you referring to? In the console it says it is disregarding this line
when "1111" => W <= NOT E15;
as unnecessary, which makes sense to an extent since there are no more cases and I have to include a with others case.