Verilog module with SPI needs to read AXI

[raff5184]

Hi,
I'm new to this topic. Basically I have a Verilog module that gets some data via SPI. I want to create an IP module in Vivado with the Verilog code and get the data from BRAM. Thus I need to use an AXI interface. How do I "convert" the SPI into AXI? I am not sure this is conceptually correct

[asmi]

Hi,
I'm new to this topic. Basically I have a Verilog module that gets some data via SPI. I want to create an IP module in Vivado with the Verilog code and get the data from BRAM. Thus I need to use an AXI interface. How do I "convert" the SPI into AXI? I am not sure this is conceptually correct

1. You don't need AXI interface to get data from BRAM. You can use the "native" interface if you wish. You can have one BRAM port connected to AXI BRAM controller, and the second port directly connected to your core. There is nothing wrong with this approach. You will still need some kind of out of band signal which would tell your core when the data is ready so that it can start transmission.
2. If you prefer to still use AXI (which would allow your core to pull the data from any AXI-compliant source, like DDR for example, and not just BRAM), you can implement AXI master interface. It's quite easy to implement, despite the fact that amount of signals you have to deal with might feel intimidating at first. Just read the AXI spec - it's very good and easy to understand. Also - Xilinx added AXI transaction viewer in the most recent version of Vivado, so debugging this interface has become easier than ever. Another extremely useful IP is "AXI Verification IP", which is basically a SystemVerilog library with full source code available, and allows you to issue and/or receive AXI transactions with very little code in test benches.
3. You can use Xilinx's "AXI Quad SPI" IP block to talk to your SPI peripheral, and a small Microblaze core to orchestrate all data transfers.