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Verilog Assign Logic to Wire Array?
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Topic: Verilog Assign Logic to Wire Array? (Read 2195 times)
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hal9001
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Verilog Assign Logic to Wire Array?
«
on:
December 23, 2023, 07:54:47 am »
I have 3 wire arrays like this
wire [3:0] a;
wire [3:0] b;
wire [3:0] c;
I want c[0]=a[0] & b[0], c[1]=a[1] & b[1], c[2]=a[2] & b[2], c[3]=a[3] & b[3]. Instead of assigning each wire manually is there a one line way to assign the logic?
Cheers!
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ataradov
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Re: Verilog Assign Logic to Wire Array?
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December 23, 2023, 08:05:49 am »
c = a & b; would do that.
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Alex
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hal9001
hal9001
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Re: Verilog Assign Logic to Wire Array?
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Reply #2 on:
December 23, 2023, 08:37:55 am »
Quote from: ataradov on December 23, 2023, 08:05:49 am
c = a & b; would do that.
Thanks
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