Universal JTAG adapter?

[kerouanton]

Hello,
In order to save space on my desk, I'm using universal programmers for EEPROM (Xgecu TL-866 II) and MCU (Segger J-Trace). However I didn't find any device able to act as an universal JTAG/SWD device for FPGAs, and I spent a few weeks looking around without success and even asked Segger support just in case).

Is anyone aware of an universal device+software suite that could be used for FPGA programming, or do I need to acquire a separate device per vendor? I'm just beggining my FPGA exploration so I don't have any hardware yet, but noticed that many of my equipment uses Spartan and Cyclone FPGAs. Segger was able to manufacture an universal programmer/debugger for MCUs, so I don't understand why it's not possible with FPGAs. Licensing issues?

Thank you for your replies.
Bruno

[darkspr1te]

openocd will act as your software and your j-link as the adapter.
openocd support text interface or gdb or tcl scripts (for uploading data for example)




darkspr1te

[RoGeorge]

Typical JTAG adapter these days is a dual channel FTDI, like FT2232H, though each FPGA manufacturer will put their own ID and/or a key inside the FTDI programmer.  In order to use the FPGA manufacturer's proprietary toolchain, you'll need to change the FTDI's ID/key accordingly for each manufacturer (which is a hack).

I'm not sure if there is a JTAG hardware supported by all FPGA manufacturers.  Since you already have working JTAG programmers, probably won't worth the effort replacing them.

If you want to try, AFAIK all the limitations regarding the JTAG capabilities are determined by reading the FTDI's EEPROM, and that content can be rewritten using the software provided by FTDI.

Most of the MCU and/or FPGA devboards already have a FTDI chip for JTAG.  By rewriting the FTDI's EEPROM (where the programmer's ID/key are stored), the devboard can be repurposed to appear as a genuine JTAG programmer for whatever FPGA manufacturer the ID/keys were written inside the FTDI's EEPROM.

[Just_another_Dave]

According to this website https://www.jtag.com/ieee-1532/, it seems that there is an IEEE standard for programming FPGAs with universal JTAG adapters. I haven’t seen many devices that claim to support it, but it might be worth checking it as it seems to be oriented towards programming many FPGAs simultaneously in complex products (which can be interesting from a manufacturing point of view, so clients might demand more ICs that support it)

[kerouanton]

Thank you for those details, I'll check that. I know OpenOCD but thanks to your post I realized it also takes care of FPGA programming (however they don't mention Xylinx, but mention Altera Cyclone, which is neat), I didn't know and believed it was only a debugger.

I'll have a try with the EEPROM hack, and let you know if it's possible.

[RoGeorge]

The JTAG standard is public, and there are many open source implementations.  See here a very brief intro for what JTAG is/does:
https://www.fpga4fun.com/JTAG1.html

However, FPGA manufacturers will usually recognize and integrate in their proprietary IDE/toolchains only certain hardware programmers they produce.

If you already have the bitstream that was built with the FPGA manufacturer's proprietary IDE/toolchain, and only need to download the bitstream into an FPGA, you can still do that using any open source JTAG SW + open hardware JTAG programmers.  But if you want to do that from inside their proprietary IDE/toolchain (and maybe use some other JTAG debugging features included in their proprietary IDE/toolchain), most probably you'll have to buy specific supported programmers from each FPGA manufacturer (or specific clones of the original hardware).

[kerouanton]

Thank you for the link, this site is great to start, that's all I wanted.

[tszaboo]

While it might be tempting to get universal programmers, I really suggest getting the vendor specific ones. There aren't too many of them, setting them up can be a PITA for the first time (and I'm sure there are people who can set it up in their dreams, I'm not one of those people). And the universal ones often times miss some feature that you want to have.

[Gribo]

There are higher end JTAG solutions from XJTAG and Corellis which support multiple vendors and product lines. But these start at few thousand dollars and go up (PXIe JTAG anyone?).

[RoadRunner]

I use same Busblaster for programming all the FPGAs I have. I have used it on Lattice, Altera and Xilinx Devices. It is FT2232 its pretty much universal USB <-> JTAG.
On Lattice and Altera Programmer directly works in IDE while I did not even tried to used IDE with Vivado, I always had Vivado scripted and Used UrJtag.

Regards

[dobsonr741]

It’s a great idea, until you hit a snag and need to pull out the vendor specific jtag/swd dongle from the drawer. Or order one. Plus, the vendor specific ones might perform better with the proprietary features. So if you up for these challenges, go for it.

[SiliconWizard]

The matter is whatever software tool you're going to use, unless you're ready to write it yourself. Use whatever JTAG adapter is supported by said tool.

As far as open-source goes, OpenOCD is one of the most actively maintained and supporting a wide range of devices. It supports a lot of different JTAG adapters as well, from FTDI-based ones as RoGeorge mentioned, to CMSIS-DAP ones, and more. So if you're ready to use OpenOCD - as long as your FPGAs are supported, you have a lot of choices and can certainly use a single adapter.

Otherwise, it depends on the software tool you're gonna use. Obviously. Both Lattice and Xilinx vendor tools support FTDI-based JTAG adapters, and there's usually nothing fancy to do to use a generic one - pretty easy.

I personally use a custom FTDI-based (FT232H) adapter for Lattice parts (with the vendor software programmer for MachXO2 devices and with ecpprog with ECP5 devices) and for Xilinx parts with xc3sprog.
I have also used a CMSIS-DAP adapter with ECP5 devices and ecpdap.

[DiTBho]

The JTAG standard is public, and there are many open source implementations.

Formed in 1985 as "Joint Test Action Group", aka "JTAG", the consortium devised a specification for performing boundary-scan hardware testing at the IC level. That was *THE* goal in 1990, and that specification resulted in IEEE 1149.1, a standard that established the details of access to any chip with a so-called JTAG port.

The documentation of the minimal protocol of JTAG as TAP State Machine and the JTAG (minimal) Physical Layer { TCK, TMS, TDI, TDO, TRST(optional) } are all fully publicly available, so it is public knowledge that

• the { TCK, TMS, TRST } input pins drive a 16-state TAP controller state machine
• the TAP controller manages the exchange of data and instructions
• the controller advances to the next state based on the value of the TMS signal at each rising edge of TCK.

All documented, and with the proper wiring, you can test multiple ICs or boards simultaneously! No problem at all here!

However, an external file, known as a Boundary-Scan Description Language, aka "BSDL file" is needed to define the capabilities of any single device’s boundary-scan logic, so when "JTAG" is used as "DEBUG PORT" to debug or mimic a CPU/FPGA/DSP, you start needing to know the "BSDL file" of the target device, and in this case the documentation is not always publicly available.

Things go even worse than that, when for example someone defines the architecture of a CPU, and then different physical CPU manufacturers: you are dealing with the same architecture (e.g. PPC4xx, e500), but you need different BDSL files, not because the CPU core is different, but rather because it happens that for commercial reasons they (e.g. IBM vs Freescale vs AMCC vs others) want to deliberately make the debug port incompatible to sell you the debug software, which ... is usually paired with a licen$e.



So, Jtag is open, if and only if, the "BDSL file" of your target is freely available. In this case, you can add support to OpenOCD or similars OpenSource softwares. Otherwise ... you have to you have to get that "BDSL file" somehow, usually through reverse engineering of a commercial ICE, going to sniff the signals issued by the host side to the Jtag TAP in order to "map" them into working patterns. It's a long and difficult job to do with LA equipment and consumes a lot of time.

[DiTBho]

[urlhttps://www.youtube.com/watch?v=TlWlLeC5BUs]here[/url]

Dave's Youtube video