Two basic GreenPAK SLG46826 SPLD questions

[zapta]

I am playing with simple SPLD design using Renesas SLG46826 and have a couple of questions. All the files of my example are here https://github.com/zapta/GreenPAKs/tree/main/blinky .

1. Let's say I add a 4 pin connector for in-circuit programming using an external programmer, with pins GND, SDA, SCK, and VCC.  Do I need to have on my board pullup/down resistors for the SDA and SCK signals and can I leave them floating?  When I experiment with an actual chip, the SLG4DVKGSD programmer provides the necessary pullups when I connect it, the programming goes through with no problem, and the chip works.


2. In my design I am using a counter cell that has two inputs, clock and reset. The clock is connected to a clock signal and the reset is left unconnected (as visualized in the design software, I don't know what is actually programmed). The simulation and the actual chip work and the Rule Checker of the Renesas design software doesn't complain. Is it safe to leave it 'unconnected' in the design?

[c64]

2. In my design I am using a counter cell that has two inputs, clock and reset. The clock is connected to a clock signal and the reset is left unconnected (as visualized in the design software, I don't know what is actually programmed). The simulation and the actual chip work and the Rule Checker of the Renesas design software doesn't complain. Is it safe to leave it 'unconnected' in the design?

My guess is if nothing is connected, 000000 will be programmed, which means ground (if you look at Connection Matrix section)