ice40 HX, A 5v tolerant FPGA ??

[nonarkitten]

It seems the HX8k has an avalanche FET clamp rather than the expected diode to VCCIO, clamping at 6.4v.

The only reason for this that makes any sense is that this is a 5v tolerant device, designed that way by Silicon Blue.

I think for Lattice this is an unwanted feature they don't include in their other devices and don't want to cloud the range by having mixed tolerance devices.

I haven't yet understood why FPGAs and CPLDs are not all made this way: with a an avalanche FET clamp rather than the expected diode 

Diodes respond better to fast transient in ESD suppression.

[spostma]

this reminds me of a similar informative discussion on Espressifs esp32 and esp8266 being 5V I/O tolerant, even if the datasheet suggests 3V3 max:
https://www.qworqs.com/2021/05/19/are-the-esp32-and-esp8266-5v-tolerant-yes-they-officially-are/

[gnuarm]

I haven't yet understood why FPGAs and CPLDs are not all made this way: with a an avalanche FET clamp rather than the expected diode 

This is a guess, but I suspect the avalanche FET clamp requires a non-trivial amount of silicon to implement. The input diodes to vcc are intrinsic (parasitic) devices, a bit like the reverse diode in a mosfet. That and there is probably near zero commercial demand as level translators can be used when 5v interfacing is required.

Yep. Guys stuck in the "vintage world" tend to think that their world is significant, but this is just a very small niche.
And level translators are plenty and cheap.

Not to mention that actually clamping to voltage rail with a simple diode is often the more desirable behavior.

They may be cheap, but they use space on the board.  My design is very tight and I will be very happy to get back the real estate from a pair of 24 pin TSSOPs.

[nonarkitten]

Indeed. CBTDs eat up a lot of board space when you're designing for size. Most of my boards fit inside a standard PLCC or DIP footprint. Having to add a CBTD per 20 IO takes up a lot of board space, quickly. Sure, you can go double sided or those microscopic DFN TI parts, but that really starts pushing up board cost and complexity.

The more I think about it, the more I question the demise of 5V as being more of a manufactured obsolescence than one born out of any particular design reason or support issue.

[gnuarm]

Indeed. CBTDs eat up a lot of board space when you're designing for size. Most of my boards fit inside a standard PLCC or DIP footprint. Having to add a CBTD per 20 IO takes up a lot of board space, quickly. Sure, you can go double sided or those microscopic DFN TI parts, but that really starts pushing up board cost and complexity.

The more I think about it, the more I question the demise of 5V as being more of a manufactured obsolescence than one born out of any particular design reason or support issue.

I seem to recall it was a power issue.  They had to dump the higher voltage so they could increase the speed without burning down the power supplies and burning up the chips.

Much the same reason they went to 2.5V, then 1.8V, 1.5V, 1.2V, etc. 

[julian1]

Any suggestions for generic level convert inputs, 5V -> 3.3V ?

Is there something better than 74LVC14A?
(Hex inverting Schmitt-trigger with 5Vtolerant input)

[woofy]

It rather depends on your definition of "better".
The 74LVC1T45FW4-7 is one option, they're cheap and effective but currently unobtainium

[dolbeau]

Any suggestions for generic level convert inputs, 5V -> 3.3V ?

To interface 5V vintage buses to a Xilinx 7-series FPGA (Artix-7), I've used successfully both CB3T family (SN74CB3T16211DGGR) devices and 74LVC2G07 for SBus, and 74LVT familiy (74LVT125PW, 74LVT245BPW) and a Xilinx XC9572XL for NuBus. NuBus has higher requirement on drive strength than SBus, hence the use of 74LVT rather than 74LVC (at least that was my understanding, I'm still quite new at this).

[SiliconWizard]

I've used the SN74LVC16245A which has 5V-tolerant inputs and works absolutely fine. With 16 channels, it's pretty cost-effective.

[julian1]

Thanks for the good suggestions. I have used '125  before for tri-state, and hct for outputs.  But didn't realize that parts with per channel tri-state and dir control were available. Using gpio to control both dir/oe is nice for flexibility. Most of the things I am looking at are ad-hoc/one-off, rather than well-organized busses.

[dolbeau]

and hct for outputs

When I investigated for my own use cases, HCT looked nice as they can output 'real' 5V (most of my solutions output TTL-compatible 3V3, so don't have a lot of margins...), but they were way too slow - I saw numbers in the 30-40ns propagation delay, on a 10 MHz bus (NuBus) it's quite high and on a 25 MHz bus (fastest SBus) it's unusable.

The CB3T have a propagation delay < 1ns, while LVC and LVT are in the 5-6 ns delay so even going through them twice is OK on a 10 MHz bus.

Currently trying to figure out if CB3T would also make do to connect an Artix-7 directly on the 25-40+ MHz bus of a 68030...

[gnuarm]

Any suggestions for generic level convert inputs, 5V -> 3.3V ?

Is there something better than 74LVC14A?
(Hex inverting Schmitt-trigger with 5Vtolerant input)

That works, but is only unidirectional.  A more universal part is a switch based level shifter.  They don't buffer, only connect the two pins through FETs.  They are much faster between the two I/O pins, sub-ns.  They limit the voltage driven through the switch because the gate drive is limited and the FET automatically turns off. 

They have a logic level enable signal, that is usually tolerant, but that needs to be verified.  No need for a DIR control since they are bi-directional.  It also makes it easy to mix directions with the same chip without getting a messy layout.

I've used the SN74CBTD3384CPW, a 10 bit part, very available.

[RoGeorge]

https://electronics.stackexchange.com/questions/97889/bidirectional-5-v-to-3-3-v-level-shifter

[nonarkitten]

Yeah, for 5V TTL, the 74CBT[D] is the way to go (that includes MOST 5V systems from the 70's and 80's). Super fast and super cheap so there's very little timing slew. Even for some CMOS designs it might be enough to just add pull-ups on the high side and call it done.

[Forty-Bot]

While reading the datasheet, I noticed under "DC Electrical Characteristics" it says

Some products are clamped to a diode when VIN is larger than VCCIO.

which likely refers to this phenomenon. Of course, it also says

IOs can support a 200mV Overshoot above the Recommend Operating Conditions VCCIO (Max) and -200mV Undershoot below VIL (Min). Overshoot and Undershoot is permitted for 25% duty cycle but must not exceed 1.6ns.

[gnuarm]

Yeah, for 5V TTL, the 74CBT[D] is the way to go (that includes MOST 5V systems from the 70's and 80's). Super fast and super cheap so there's very little timing slew. Even for some CMOS designs it might be enough to just add pull-ups on the high side and call it done.

If timing is of concern, the switches are the way to go.  They aren't buffers, they are just FET transistors acting like a wire.