tRAS definition for DDR memory

[promach]

In Figure 3 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh , why tRAS is defined as the max timing between two REFRESH commands ? This seems contradicts with Micron document.

[AndyC_772]

The Micron data sheet is for a DDR3L device, but the System Verilog spec is talking about a feature added to DDR4.

Are you sure you're comparing like with like?

[SiliconWizard]

Yes this isn't the same type of memory. But I can't see any mention of "tRAS" in figure 3 of the page you mention anyway?

[asmi]

9 * tREFI is the upper bound of tRAS, basically it's the absolute maximum time a row can be held open. 9 * REFI is because of this:

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be posted to any given DRAM, meaning that the maximum absolute interval between any REFRESH command and the next REFRESH command is nine times the maximum average interval refresh rate.

[promach]

@asmi  but Micron document defines tRAS as the timing between ACTIVATE command and PRECHARGE command.

@SiliconWizard  look at the Micron document on the left of the picture

[SiliconWizard]

@SiliconWizard  look at the Micron document on the left of the picture

tRAS is mentioned in the Micron DS, not on the figure you mention. At least not directly. So that was confusing. And I think you got confused too.

asmi gave you the answer. max tRAS is 9xtREFI, just because a longer tRAS would violate the refresh requirements. So that's not contradictory.

[promach]

a longer tRAS would violate the refresh requirements.

Could you be more SPECIFIC on which exact refresh requirements ?

[asmi]

@asmi  but Micron document defines tRAS as the timing between ACTIVATE command and PRECHARGE command.

Yep. The row is opened by ACTIVATE command and stays open until you issue PRECHARGE command (either explicitly, or implicitly via auto-precharge flag of read/write commands). Since you need to precharge all rows before you can issue a REFRESH command, the maximum allowed interval between refresh commands places an upper bound on how long the row can stay open.

[promach]

there should be a value inside the MAX column for tRC for the Micron document though ?

When I searched online about tRC, why the following mentioned that no PRECHARGE is allowed in between ?

[promach]

how shall I understand Figure 4 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh ?

if there are 8 REF-Commands postponed, then it should be 7 x tREFI instead of 9 x tREFI