FPGA USB3.0 Mass Storage mode?

[seyedsaeed]

Hello
I want to create a USB3.0 mass storage with FPGA.
required pieces:
4GB RAM of lpddr type
USB 3.0 external PHY or internal PHY
please guide me.

[tom66]

This is one of the broadest specifications available.  It sounds like a student project.

You need to specify what FPGA you want to use, or if you don't have an FPGA in mind that needs to be decided.

USB3.0 requires high speed PCB design and most FPGAs that can support USB3.0 are expensive and in large packages (Xilinx Ultrascale Zynq for instance).

You will need to determine if you want to go baremetal or Linux with gadget mode drivers.

There is no explicit requirement for 4GB of RAM to support USB3.0, so I wonder if you have a reason for stating that.

[SiliconWizard]

That's insane. There are dedicated controller ICs that will do just that, properly.

But what is this mass storage about? You're talking about RAM but not permanent storage at all. Is this something to emulate a mass storage device but only RAM-based, maybe? (Which would explain why of-the-shelf controllers would not cut it.)

If so, then using some ARM SoC will be much easier than a FPGA, yes.

If this is a student project, then it sounds pretty ambitious. If it absolutely has to be a FPGA, then using a FX3 for implementing the USB side would make it much easier. But in that case, the FX3 would implement the mass storage USB device and would provide a FIFO interface to the FPGA, which would just handle read/write requests and implement the DDR controller. Still sounds like a lot of work.

[seyedsaeed]

This is one of the broadest specifications available.  It sounds like a student project.

You need to specify what FPGA you want to use, or if you don't have an FPGA in mind that needs to be decided.

USB3.0 requires high speed PCB design and most FPGAs that can support USB3.0 are expensive and in large packages (Xilinx Ultrascale Zynq for instance).

You will need to determine if you want to go baremetal or Linux with gadget mode drivers.

There is no explicit requirement for 4GB of RAM to support USB3.0, so I wonder if you have a reason for stating that.

No, this is not a student project.
I am in the early stages of research and I don't know which method or which FPGA is suitable.
I should be able to use a 4GB lpddr ram at 400mhz to 1.5ghz.
I need to use USB 3 to exchange data between the computer and the circuit in mass storage mode.
I know that RAMs are volatile memory, but RAM must be used for storage.

[seyedsaeed]

That's insane. There are dedicated controller ICs that will do just that, properly.

But what is this mass storage about? You're talking about RAM but not permanent storage at all. Is this something to emulate a mass storage device but only RAM-based, maybe? (Which would explain why of-the-shelf controllers would not cut it.)

If so, then using some ARM SoC will be much easier than a FPGA, yes.

If this is a student project, then it sounds pretty ambitious. If it absolutely has to be a FPGA, then using a FX3 for implementing the USB side would make it much easier. But in that case, the FX3 would implement the mass storage USB device and would provide a FIFO interface to the FPGA, which would just handle read/write requests and implement the DDR controller. Still sounds like a lot of work.

No, this is not a student project.
I am in the early stages of research and I don't know which method or which FPGA is suitable.
I should be able to use a 4GB lpddr ram at 400mhz to 1.5ghz.
I need to use USB 3 to exchange data between the computer and the circuit in mass storage mode.
I know that RAMs are volatile memory, but RAM must be used for storage.
FX3 is expensive although it offers good features.

[magic]

USB 3.0 and USB Storage Class specifications are freely available. Read them, implement them, problem solved.

Or, read them, realize that it will take many man-hours to implement them, buy a USB 3.0 FIFO chip and forget about mass storage.
Or buy IP cores for a CPU and peripheral-capable USB controller which can run Linux or other software with existing mass storage support, if adding chips is unacceptable.

[seyedsaeed]

USB 3.0 and USB Storage Class specifications are freely available. Read them, implement them, problem solved.

Or, read them, realize that it will take many man-hours to implement them, buy a USB 3.0 FIFO chip and forget about mass storage.
Or buy IP cores for a CPU and peripheral-capable USB controller which can run Linux or other software with existing mass storage support, if adding chips is unacceptable.

Which usb 3 fifo and FPGA do you recommend?

[glenenglish]

Use a XIlinx FPGA that has a native USB3.x capable transceiver on chip - just add some bypass caps and bootlflash , u can get away with just 3 supply rails...

you dont even need ram because there is enough inside. (but if you need more, there are 64 bit wide hard controllers on chip)

use a Xilinx #  ZU15EG., probably in the 'B1156' type package, should be enough interfaces for you.  It has enough for four native USB3 interfaces plus  16 x SERDES and a 100Gb ethernet PHY

the technical reference manual is here
here is the USB3 page  :
https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/USB-Controller
I would recommend this option, there is a 64bit AXI interface to the PS
full manual
https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm

if the ZU15EG is too big, try a ZU1CG in a 484 or a 530 package. Sure, it lacks the 36MB of Ultraram, and it doesnt have the 100 Gbit ethernet phy, but it does have four USB3 native interfaces and a 64 bit RAM hard interface you'll need for that memory....

[seyedsaeed]

Use a XIlinx FPGA that has a native USB3.x capable transceiver on chip - just add some bypass caps and bootlflash , u can get away with just 3 supply rails...

you dont even need ram because there is enough inside. (but if you need more, there are 64 bit wide hard controllers on chip)

use a Xilinx #  ZU15EG., probably in the 'B1156' type package, should be enough interfaces for you.  It has enough for four native USB3 interfaces plus  16 x SERDES and a 100Gb ethernet PHY

the technical reference manual is here
here is the USB3 page  :
https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/USB-Controller
I would recommend this option, there is a 64bit AXI interface to the PS
full manual
https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm

if the ZU15EG is too big, try a ZU1CG in a 484 or a 530 package. Sure, it lacks the 36MB of Ultraram, and it doesnt have the 100 Gbit ethernet phy, but it does have four USB3 native interfaces and a 64 bit RAM hard interface you'll need for that memory....

Does this have a minimum cost?

[glenenglish]

You can buy a Zu1CG in a 530 package for about $95 for 100 pcs

If you have budget or time constraints, I suggest you go with the FX3 chip like the others suggested.

I suggest you buy a Cypress FX3 evaluation kit,

here is the kit

https://www.infineon.com/cms/en/product/evaluation-boards/cyusb3kit-003/

[seyedsaeed]

You can buy a Zu1CG in a 530 package for about $95 for 100 pcs

If you have budget or time constraints, I suggest you go with the FX3 chip like the others suggested.

I suggest you buy a Cypress FX3 evaluation kit,

here is the kit

https://www.infineon.com/cms/en/product/evaluation-boards/cyusb3kit-003/

Cypress FX3 cant support lpddr4

[SiliconWizard]

You can buy a Zu1CG in a 530 package for about $95 for 100 pcs

If you have budget or time constraints, I suggest you go with the FX3 chip like the others suggested.

I suggest you buy a Cypress FX3 evaluation kit,

here is the kit

https://www.infineon.com/cms/en/product/evaluation-boards/cyusb3kit-003/

Cypress FX3 cant support lpddr4

Which is why I suggested connecting one to the FPGA, which will handle the LPDDR4 memory.
The reason for this setup is that it will be much easier to implement the USB side this way. Doing it directly on FPGA using a USB 3 SS PHY will be a nightmare if you're not familiar with that.
Or maybe you can use one of these hybrid FPGAs (with FPGA fabric + some ARM hard core), which should also make things easier, as long as there's available code for the USB side, otherwise you're up for a pretty long journey.

[seyedsaeed]

You can buy a Zu1CG in a 530 package for about $95 for 100 pcs

If you have budget or time constraints, I suggest you go with the FX3 chip like the others suggested.

I suggest you buy a Cypress FX3 evaluation kit,

here is the kit

https://www.infineon.com/cms/en/product/evaluation-boards/cyusb3kit-003/

Cypress FX3 cant support lpddr4

Which is why I suggested connecting one to the FPGA, which will handle the LPDDR4 memory.
The reason for this setup is that it will be much easier to implement the USB side this way. Doing it directly on FPGA using a USB 3 SS PHY will be a nightmare if you're not familiar with that.
Or maybe you can use one of these hybrid FPGAs (with FPGA fabric + some ARM hard core), which should also make things easier, as long as there's available code for the USB side, otherwise you're up for a pretty long journey.

Is it possible to implement ram communication without ip core in a smaller fpga?

[glenenglish]

What is the RAM for?

Please describe precisely and honestly your application .

[seyedsaeed]

What is the RAM for?

Please describe precisely and honestly your application .

RAM to store data only when connected to power
We require data storage up to 4 GB and only while the power is connected.

[agehall]

We know how RAM works. What data do you intend to store in it and why? Why can’t you just stream the data without a huge buffer? Elaborate on what your thing is for so people can give suggestions that matters.

[SiliconWizard]

What is the RAM for?

Please describe precisely and honestly your application .

RAM to store data only when connected to power
We require data storage up to 4 GB and only while the power is connected.

Is this meant to become a product, or is it for "internal" use?

As some of us have suggested earlier, the easiest path is probably going to be using a SoC that already supports at least 4GB of RAM, and if you don't need to make a large series of them, buying an off-the-shelf SBC would be easier yet.

After that, all you'll need is configure it to act as USB device on one of its USB ports, which I'm sure people have done already on boards such as the RPi.

[glenenglish]

Buy this board : . it has a native USB3 interface on the fpga (not a glue chip)  and plenty of RAM, and linux out of the box.

MYIR make good stuff, and china will ship to Iran even with a export ban LOL .
this is the cpu module-  it has 4GB of LPDDR4 and this board works.

and you buy the eval base board for this requirement wher eyou get a cpu board
https://www.myirtech.com/list.asp?id=713
https://www.myirtech.com/list.asp?id=712

[seyedsaeed]

What is the RAM for?

Please describe precisely and honestly your application .

RAM to store data only when connected to power
We require data storage up to 4 GB and only while the power is connected.

This project is from the employer.
This project is going to be produced.
I've been asked to investigate the cheapest way to get a mass storage controller on RAM and design one with the following in mind:
1- USB 3 connection
2- Using RAM as a place to store information
3- It should be recognized as a mass storage controller by connecting to the computer

Is this meant to become a product, or is it for "internal" use?

As some of us have suggested earlier, the easiest path is probably going to be using a SoC that already supports at least 4GB of RAM, and if you don't need to make a large series of them, buying an off-the-shelf SBC would be easier yet.

After that, all you'll need is configure it to act as USB device on one of its USB ports, which I'm sure people have done already on boards such as the RPi.

[glenenglish]

so, like a $5  USB FLASH memory storage device key , except it is RAM ? battery backed RAM ?
but why? does the host not have any RAM ??

what's wrong with a big SSD? A big SSD will likely have a few gigabytes of RAM cache.....