The FPGA will do some DSP and one way or another reduce the data bandwidth going on to a CPU.
it depends on what DSP you're want to do. For example if your ADC running at 100 MHz clock, most FPGA will be unable to apply 1024 tap FIR filter at full speed, because there is a lack of hardware multipliers and FPGA speed limitations. So, you will needs to use CIC filter before FIR filter in order to reduce computation cost. It will add some limitations on DSP dynamic range, signal purity and frequency selection. You're needs to know your DSP structure to estimate your needs.
Also it very depends on ADC dynamic range. Since high dynamic range ADC needs more bits for processing, your FPGA will needs more resources to implement DSP blocks. For example I'm using 14-bit ADC running at 100 MHz, and CIC filter that I use needs to use 86-bit registers and more in order to avoid overflow.
Usually DDC/DUC DSP eats about 5-20 kLE (depends on your needs). Also you will need some high speed interface, like GMII, so you're needs to add about 3-5 kLE for GMII, ARP, DHCP and UDP stack implementation.
Also, note that different ADC using different output interfaces (serial/parallel, different logic levels standard), so make sure your FPGA is compatible with ADC output and can handle it with no limitations.