[FPGA] From zero to DVB parsing

[jack burton]

This is the board i'll interface with, the connector P1 is the one that brings out the 8-bit TS for the FPGA board.
Actually the board uses a stm32f7 to control the NIC (STV0910) via i2c interface.


Looking forward to the development, assuming that i could parse a TS, what do i need to test the algoritm ?
I was wondering if there's a way to simulate it using a TS file recorded with a DVB-S2 tuner on a PC ?

[Scrts]

This is the board i'll interface with, the connector P1 is the one that brings out the 8-bit TS for the FPGA board.
Actually the board uses a stm32f7 to control the NIC (STV0910) via i2c interface.


Looking forward to the development, assuming that i could parse a TS, what do i need to test the algoritm ?
I was wondering if there's a way to simulate it using a TS file recorded with a DVB-S2 tuner on a PC ?

Possible, but with some pain. E.g. it is possible to play .TS file from VLC over network, then you can receive that stream with FPGA and extract from UDP/RTP frames. It is straightforward, if you only need the tables, but would be way more complex if you'd need the video as Program Clock Reference (PCR) tracking is extremely important there.

[jack burton]

This is the board i'll interface with, the connector P1 is the one that brings out the 8-bit TS for the FPGA board.
Actually the board uses a stm32f7 to control the NIC (STV0910) via i2c interface.


Looking forward to the development, assuming that i could parse a TS, what do i need to test the algoritm ?
I was wondering if there's a way to simulate it using a TS file recorded with a DVB-S2 tuner on a PC ?

Possible, but with some pain. E.g. it is possible to play .TS file from VLC over network, then you can receive that stream with FPGA and extract from UDP/RTP frames. It is straightforward, if you only need the tables, but would be way more complex if you'd need the video as Program Clock Reference (PCR) tracking is extremely important there.

I was thinking to something like simulate the IP with modelsim giving the file as input, feeding the fpga model with 8 bit bus extracted from the file.

[rstofer]

You may find this book helpful:

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

[jack burton]

You may find this book helpful:

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

thank you Rstofer

[Scrts]

This is the board i'll interface with, the connector P1 is the one that brings out the 8-bit TS for the FPGA board.
Actually the board uses a stm32f7 to control the NIC (STV0910) via i2c interface.


Looking forward to the development, assuming that i could parse a TS, what do i need to test the algoritm ?
I was wondering if there's a way to simulate it using a TS file recorded with a DVB-S2 tuner on a PC ?

Possible, but with some pain. E.g. it is possible to play .TS file from VLC over network, then you can receive that stream with FPGA and extract from UDP/RTP frames. It is straightforward, if you only need the tables, but would be way more complex if you'd need the video as Program Clock Reference (PCR) tracking is extremely important there.

I was thinking to something like simulate the IP with modelsim giving the file as input, feeding the fpga model with 8 bit bus extracted from the file.

Yes, this is the good way to do it as well - feed TS file using textio library. You will have to generate TS_Start yourself though.