shocked, how can a 60Mhz pixelclock LCD have 50PIN 24Bits TTL interface?!?

[DiTBho]

I have always seen LCDs with pixel clocks higher than 40Mhz using FPD-Link to transfer high speed digital video.

• FPD-Link uses LVDS - Low Voltage Differential Signalling - which transmits bits of data as differences in voltages between the 2 twisted pair wires
• LVDS reduces the generation of electromagnetic noise, and due to the twisted pair cables and differential signalling, is resistant to common mode noise as well

Look at the attached datasheet: how is it possible that there are 1024x600800 LCDs with 50PIN 24Bits TTL interface?!? 


edit:
typo

[EugenioN]

A 14ns parallel bus over a couple of inches is still quite manageable: you need to equalize all the signal traces length and constrain the fpga design.

Going differential and keep a small connector would require a more complex lcd embedded electronic at an increased cost.

[DiTBho]

A 14ns parallel bus over a couple of inches is still quite manageable: you need to equalize all the signal traces length and constrain the fpga design.

worse still, it's used with a 40cm-long cable

[DiTBho]

I just don't understand how it could work!

[EugenioN]

Maybe with mighty, well decoupled ttl drivers  and some trickery for clock/control signals constraining picoseconds tuning until it works in the required environment.

And, of course, a fair amount of luck and positive engineering attitude ;-)

[Mahagam]

At 50MHz you have a 20ns period. Let take 10% of it as the tolerance. 2ns * speed_of_light is more than half of the meter.

[BrianHG]

With proper termination and at least 1 gnd pin for every 2 data lines, even better 1 gnd to 1 data, you can easily achieve 75mhz ttl data transfer.  40mhz pixel clock, 20mhz bandwidth for data is a piece of cake.

I've done 150mhz 3.3v ttl over 0.5 feet of flex cable.

*Double check, your panel may need series termination on the driver side to minimize signal bounce and EMI.
Modern designs may choose series term. since it uses less power relying on the capacitance of the inputs on the panel's chipset.

[jahonen]

There are only really 4 things in the transmission path per Howard Johnson which affect the signal integrity thus determine if the interface works or not: 1) impedance 2) attenuation 3) delay 4) crosstalk. Which of these you think is the problem with the 60 MHz interface? Getting it to work is not that difficult. The only signal that needs to be really clean is the dot clock as it is asynchronous. All the other sync and 24 RGB signals need just to stabilize before the latch edge of that dot clock. Otherwise they can bounce around in any way they like.

That said, this kind of interface is really terrible for EMC. Look at the display pinout. There are just few ground pins. Just put a 1 pixel black-1 pixel white vertical stripe pattern on the display (that makes all those 24 RGB signals do a in-phase square wave) and go measure it. Good luck meeting the EMC requirements in this particular case The reason is that there are just not enough return paths for all those data signals, and it really bumps up radiated emissions.

Regards,
Janne

[tggzzz]

Look at the attached datasheet: how is it possible that there are 1024x600800 LCDs with 50PIN 24Bits TTL interface?!? 

It is not a TTL interface, it is a CMOS interface with the traditional input levels of 0.3Vcc and 0.7Vcc.

Presumably the input load is a CMOS load, i.e. ~5pF.

Hence the transmission line in the ribbon cable will presumably be source-terminated. Basic transmission line theory indicates that the transitions will have completed after the signal has propagated 80cm, i.e. around 4ns.

The setup and hold times are symmetric, both being 5ns. Hence the inputs must be stable for 10ns total.

The DCLK is next to a GND, so its impedance will be controlled. Given the above timings, the data signals should be stable at the DCLK transition.

The most unpleasant feature I see is only 4 GND lines in the cable. Provided the received DCLK signal is clean and other signals have become stable, at a quick glance I don't see a major problem.

[mzzj]

Back in the dark age Parallel ATA was running up to 133Mhz with 5v logic?

[DiTBho]

this kind of interface is really terrible for EMC

It seems that there are some GNU/linux SCB(1) that interfaces directly with that kint of LCD, which leaves me astonished also for the EMI issue...
They shoudlnt' be advertised as "industrial SBCs", at most they can be "hobbyist SBCs" ... 

But, let me understand: the reason why all laptop and industrial panel LCDs use LVDS as PHY?
Compared to parallel connection, with LVDS@FPD-Link it sounds easier
+ to meet EMI requirements
+ to have a connection cable with fewer lines (about 10, against 50)
+ to be able to have a cable that passes through a hinge

Correct? are these the reasons?

(1) e.g. Beaglebone Black

[DiTBho]

Back in the dark age Parallel ATA was running up to 133Mhz with 5v logic?

yes, I remember it.
However, I also remember that it used a special cable, which alternated a ground wire with each given data wire.
The cable I showed above does not use these precautions, and it's the suggested cable to connect the LCD to the Linux SBC.

[DiTBho]

Basic transmission line theory

Can you suggest a book or something to study these things?

[tggzzz]

Basic transmission line theory

Can you suggest a book or something to study these things?

Innumerable application notes from many manufacturers. TI is a good starting place. 30-40yo app notes were around the time when every TTL designer had to understand and deal with the issues. (ECL hit the problem earlier; see Motorola ECL app notes)

TAoE3, section 12.10 compares many standards.
TAoE3 appendix H.

[SiliconWizard]

Back in the dark age Parallel ATA was running up to 133Mhz with 5v logic?

yes, I remember it.
However, I also remember that it used a special cable, which alternated a ground wire with each given data wire.

At those frequencies yes, but AFAIR up to 33MHz was no problem using normal 40-pin cables and that worked with cables that could easily reach 1m.
60MHz over 40cm should not cause major issues. Apart from EMI, especially at 5V. Must be pretty horrific. But back then that wasn't as much of a concern, and also everything tended to be put inside large (and heavy) metal shields.

[glenenglish]

There's no problem with that interface , or interfaces twice as long and twice as fast on that cable

Suggest pick up a copy of Howard Johnson's book. High Speed Digital Design

https://www.abebooks.com/servlet/BookDetailsPL?bi=31936636576&dest=aus&ref_=ps_ggl_21018577892&cm_mmc=ggl-_-AU_Shopp_ISBN-_-product_id=COM9780133957242USED-_-keyword=&gclid=Cj0KCQjwwae1BhC_ARIsAK4JfrxRNvPxTtWXzFDEg8wFLIKJ8N9zNG1ymvRp0Bgj7L_47KRQNjlYnXIaAh7HEALw_wcB

[DiTBho]

Suggest pick up a copy of Howard Johnson's book. High Speed Digital Design

• High Speed Digital Design: A Handbook of Black Magic
  by Johnson, Howard, Graham, Martin
  ISBN 10: 0133957241
  ISBN 13: 9780133957242

I used a book coupon. 20% off.
just bought my hardcover copy on Amazon 

[DiTBho]

But, let me understand: the reason why all laptop and industrial panel LCDs use LVDS as PHY?
Compared to parallel connection, with LVDS@FPD-Link it sounds easier
+ to meet EMI requirements
+ to have a connection cable with fewer lines (about 10, against 50)
+ to be able to have a cable that passes through a hinge

Correct? are these the reasons? 

[DiTBho]

Assuming you don't need colors, and that only one bit

         bit[{1,0}]={green, black}

is fine, then assuming you ground the entire red and blue line, and short-circuit all the greens

Code: [Select]

r0=r1=r2=r3=r4=r5=r6=r7 = gnd
g0=g1=g2=g3=g4=g5=g6=g7 = pixel_data
b0=b1=b2=b3=b4=b5=b6=b7 = gnd

in addition to reducing the data lines (and also the PCB), it should also improve the EMI situation.

Since, in this way, there would be more ground return lines than signals on which the pixel data travels

What do you think? 

[nctnico]

If the display has been designed this way, I'm sure the designers are well aware of the limitations and have dealt with potential issues. The signal lines in the display likely have some form of termination to deal with reflections. Just connect it as outlined in the datasheet and all will be fine. Just don't connect it with a cable that is longer than needed and make sure the display's chassis is grounded to the same ground as the driver board's ground. This will take care of many potential EMI issues.

[BrianHG]

Just use series resistor termination, I would use 4x resistor packs, something like 100ohm for 20mhz data, 50ohm for the 40mhz clock.  If you are using a FPGA, use IOs from one bank and make sure you can set output current drive strength, which basically give you an equivalent series termination scrapping those series resistors.  Also, for FPGAs, use a clock output where if necessary in post, you can tune either the clock output phase, or relative data output phase.

[bmxsesh]

Are you saying LCDs can be overdriven at frequencies higher than in the specs?
My display has 27MHz clock but I am trying to do just-in-time processing from CCD image sensor and vertical porches are significantly higher (187 lines vertical sync total on the display, versus 43 vertical sync on the CCD)

[c64]

Are you saying LCDs can be overdriven at frequencies higher than in the specs?

I remember playing with some LCD, maximum clock in datasheet was around 80MHz. I managed to run it at 110

[DiTBho]

it would be interesting the other way around: if the datasheet says that the pixel clock is 40Mhz for a refresh rate of 60Hz, what happens if you use a pixel clock of 20Mhz?

three possible things can happen, in my opinion:

• the display continues to work, the refresh rate  is still enough for human eyes and in text mode you don't notice any annoying flickering, whereas playing video is not good
• the display continues to work, but you notice a very annoying flickering even in text mode, due to a very low refresh rate
• the display no longer shows anything

[DiTBho]

But, let me understand: the reason why all laptop and industrial panel LCDs use LVDS as PHY?
Compared to parallel connection, with LVDS@FPD-Link it sounds easier
+ to meet EMI requirements
+ to have a connection cable with fewer lines (about 10, against 50)
+ to be able to have a cable that passes through a hinge

Correct? are these the reasons?

no one answered this question