Renesas "lowest cost" ForgeFPGA low-density FPGA - free eval boards

[ataradov]

I'm no longer excited.

I was excited 3 years ago when this was first announced. It is now 3 years later, still no chips and the new promised chips are not what was promised originally.

The real talk will start when there are actual chips available. If they end up costing way more than promised, then this is DOA except for whatever real large volume customers they have.

There will be boards with ICs soldered on them and they will be much cheaper. The current even boards are expensive because they use expensive sockets. And the device is pretty simple, you probably don't even need an eval board.

[glenenglish]

The FPGA effort by renesas is a bit of a joke.
I maintain  its for some internal requirement, they really cant be serious about being an fgpa supplier ?!?!
Maybe a thought bubble. Maybe their FPGA is one from TinyTAPEOUT ? lol

@ slburris : Efinix have a 3.3V capable FPGA  in a 100/144 QFP - the Trion series T20 is a fair chunk of FPGA
The T20 in a 100 TQFP also has on board 16MB flash memory chip, saving wiring....
The tools are quite OK. basic but they do the job without surprises.
https://www.efinixinc.com/docs/trion-selector-guide-v3.3.pdf
https://www.efinixinc.com/docs/trion20-ds-v5.7.pdf

[ataradov]

T20 is not in the same market as ForgeFPGA. On a 100 pin package, it uses half the pins for power supplies and configuration. And a lot of other pins are configuration straps that have specific pull-up/down requirements. They also have core supply with specific sequencing requirements with respect to VDDIO. The amount of support components is maddening.

ForgeFPGA is more of a continuation of Silego Greenpak devices - a simple replacements for a bunch of logic ICs.

[glenenglish]

Alex, you have used Efinix ? I've found the  supply sequencing on Trion  didnt matter at all (apart from Vcore first, then everything else) .... as long as everything was stable quickly  before  config begins.... easy enough to sequence core then vccio, just use the power-good from Vcore regulator for Vccio Enable. that is not difficult . the 144 QFP yes has more IO available...   

But I take your point that its not a PLD glue logic size FPGA, more like a "real FPGA" (that you can run a soft core on).
Yes, an easy-to-use fpga has 1 supply rail , and internal  flash config and jtag.
My point was Efinix Trion is a modern FPGA with modern tools AND a QFP, not some relic from the 2000s (Spartan6) with unsupported tools.
Lattice has some QFPs

[ataradov]

Alex, you have used Efinix ?

I just made the board with T20. Have not used them in practice yet. I made a board out of curiosity. And the whole way I was annoyed by their configuration pins.
But I like the IDE that you can download and continue to use without requesting a license every 6 months.

(apart from Vcore first, then everything else)

But that is still a requirement, so something that required additional components to sequence. Surprisingly, this sort of sequencing is what Greenpak and ForgeFPGAs are designed for.

the 144 QFP yes has more IO available...   

But also requires a huge board area.

Yes, an easy-to-use fpga has 1 supply rail , and internal  flash config and jtag.

This is why I use Lattice MachXO2 HC. Single supply, plenty of I/O in a full range of pin counts.

My point was Efinix Trion is a modern FPGA with modern tools AND a QFP, not some relic from the 2000s (Spartan6) with unsupported tools.

Well, it would be great if they could take pin assignments from SDC files instead of some goofy GUI tool. And not supporting tri-state pins  directly is also not very "modern".

Also, their IDE is very strange. They have the central widget set to be the log, so your editor is forced to be on a side panel. I guess they don't expect anyone to actually use their editor, just like most FPGA IDEs.

[glenenglish]

agreed.
although "But also requires a huge board area.". well you cant please everybody !

I do like Lattice MACHX02.... great combination of features.

Alex do you know if any of those flash based Lattice parts can reconfigure themselves from a bitstream once they are running I need to have the fpga start on the internal flash config and then load a new config from a RS485 serial connection to a host.

because -
I'm looking at doing  a (maybe) T20 in a front panel of a remote panel device.....- the on-chip flash memory gets it going (initial display  and IO config) )   and the part then waits for the 'running'  config file download on the RS485  serial wires that connect it to the 'main unit'. That way the front panel always has the correct (matching) firmware as the main control unit. .....On Trion, I would need to program a SPI FRAM , and then set a config bit and retrigger configuration from the SPI device. might work.... Efinix  Titanium would be easier, since it can do a reconfig from a bitstream while operating . But no QFP for Ti

[SiliconWizard]

Alex do you know if any of those flash based Lattice parts can reconfigure themselves from a bitstream once they are running I need to have the fpga start on the internal flash config and then load a new config from a RS485 serial connection to a host.

Yes of course. They are still SRAM-based (contrary to the Actel Igoo series, IIRC) and can be reconfigured at any point (without reprogramming the internal flash) via JTAG.
But if by "themselves", you mean without JTAG, then, the answer is, I think, no.

If you're gonna do what you describe above, your best bet is to do this from a small MCU (or your main MCU if there is any on your board) which will handle the RS485 communication, check integrity of the bitstream (always a plus), and upload it to the FPGA SRAM via JTAG. Benefit is that the code for doing this will be, for a large part, FPGA-agnostic and will be reusable. You'll only need to port a small section of MCU code for each FPGA.

[ataradov]

Alex do you know if any of those flash based Lattice parts can reconfigure themselves from a bitstream once they are running I need to have the fpga start on the internal flash config and then load a new config from a RS485 serial connection to a host.

As far as I know it is not possible. They don't support partial reconfiguration and full reconfiguration would erase the SRAM. You can update the flash from the FPGA logic, but if you need this to be highly dynamic, it will wear out the flash fast.

They do support reconfiguration from the external SPI flash. I have not looked into the specifics, but the same FRAM might work. You would need to store the received bitstream somewhere anyway.

The configuration method is selected thought the NVM fuses, so it might be tricky to switch in run-time.

There is also a dual-boot mode with a fail-safe image. But it might not be as useful, since the "safe" image is stored in the external device and it always tries to configure from the external device first.

In general with updates like this, it might be easier to have a small external MCU to load the new bitstream over JTAG. Let FPGA configure from the safe internal flash, receive the new image, tell the MCU to reconfigure with the new image over JTAG.

And unlike flash configuration over JTAG, SRAM configuration is very easy.

[slburris]

@ slburris : Efinix have a 3.3V capable FPGA  in a 100/144 QFP - the Trion series T20 is a fair chunk of FPGA

I have not looked at Efnix parts.  I'll have to study the datasheet. 

Since I can get the Spartan 6 for $6-7, I'd like to find something less than that for smaller use cases, and have it commonly
available and in stock (dk/mouser).  While I'm stuck with ISE, I'm at least familiar with its quirks.  I've used Vivado (for S7 and Artix 7),
and it's an entirely different set of quirks!

I did a couple of projects a few years ago with the MachX02 1200, and it was pretty easy to use.  Maybe I should revisit them.
Huh, actually, I can get the LCMXO2-1200HC-4TG144C for $2.61 qty 1, that's nicely in the "cheap" category.

[ataradov]

Huh, actually, I can get the LCMXO2-1200HC-4TG144C for $2.61 qty 1, that's nicely in the "cheap" category.

Where? This is a highly irregular price even for chap sources. I would not rely on getting it at that price consistently.

[slburris]

Huh, actually, I can get the LCMXO2-1200HC-4TG144C for $2.61 qty 1, that's nicely in the "cheap" category.

Where? This is a highly irregular price even for chap sources. I would not rely on getting it at that price consistently.

At LCSC: https://www.lcsc.com/product-detail/Programmable-Logic-Device-CPLDs-FPGAs_Lattice-LCMXO2-1200HC-4TG144C_C1521637.html

I order a lot from them, so I'll probably just toss 10 or 20 of them into my next order of other parts. 

[glenenglish]

https://www.digikey.com/en/products/detail/efinix-inc/T20Q100F3C3/19100262

includes on package flash chip for USD$9   qu 1

T20 can run a fair size RISC-V  (efinix supply canned IP) and has a megabit of block ram.

However ! if you want a small, single power pin FPGA, MACHX02 is hard to beat......
the larger ones can run a small microcontroller....

[glenenglish]

back to the Renesas (as the T20 above is 20x the size)

Let's apraise the datasheet

OK so it is low power when it's doing nothing  : 50uA at room temperature.  1mA at 85C

BRAM clock freq : 87 MHz at 25 degc, 45MHz at 85C
what's the story with this silicon process? It's like its made with Z5U / Y5V dielectric.....

32 bit counter : 56MHz at room temperature. no speed demon.

FF to LUT- FF  : 182 MHz room temp. yeah well that's not too bad I guess

has a 5 input LUT/FF, (1120 of those) ---- they are formed as fractuable 6 input LUT and dual FF, in a CLB array of four of those.

reading how the shift registers are implemented,  and the terminology used , you'd think you were reading a Xilinx manual.

That the CLBs can be used as distributed memory is good.

The block rams are are oK with basic features like variable aspect ratio etc, 16kb in size.

If this was a 0.8mm QFP32 and ran 3.3V, it would be a a good option for many.

Wonder what the tools do ? Does it use / based  the open source toolchains ? etc like ICE40 ? Gatemate ?

Gatemate is cool.

I cannot see how this competes in a world where ICE40  is so easy , available, known toolchains and works
although, for the number of LUTs, it does have more multipliers and ram  resources compared to an ICE40
other options- largest MACHXO3 device in a QFP is MachXO3LF-2100  (100QFP) and 3.3V core. GOWIN has QFP.

[ataradov]

At LCSC

I would not rely on that price long term. LCMXO2 availability on LCSC is really spotty. They come and go fast.

[ataradov]

Wonder what the tools do ? Does it use / based  the open source toolchains ?

Yosys for synthesis and a custom P&R tool. We investigated that in detail in the other thread.

Their "project" contains all the source code. There are no separate Verilog files. Your project is one self contained file. They do it so that you can send that project to the factory for mass programming, which seems like their main goal here.

This also has a potential to be a version control nightmare.

FF to LUT- FF  : 182 MHz room temp. yeah well that's not too bad I guess

I would be very skeptical of those clocks. Because it is using Yosys, there is no timing-driven synthesis or timing constraints of any sort. You just get what you get.

[glenenglish]

what ? so its up to the designer to count the number of logic levels in series to figure out of something will meet timing ??

[ataradov]

I think the tools are designed to meet internal timings and just report the maximum frequency for the design. But there is no way to specify setup/hold times for the I/O pins.

Again, the idea here is not performance, but simplicity. And they probably wanted all those things, but it is just not in the OSS tools and they don't want to invest resources to implement it.

This is the same thing you get with ICE40. So, I guess it can work, but does not really make me feel good putting that into mass produced things.

[SiliconWizard]

I think the tools are designed to meet internal timings and just report the maximum frequency for the design. But there is no way to specify setup/hold times for the I/O pins.

Yes, that's one limitation of the yosys toolchain - I don't know if they use nextpnr for PAR (or a derivative thereof), but nextpnr, last I checked, indeed didn't allow specififying any timing constraints for IOs. Which is a bummer.

[glenenglish]

except as a teaching tool how could one ever  time anything ..  (and because it doesnt teach about timing, I wonder just how useful ??)  OH ok so it times internal paths. right. yes.... but not to the IO pin

I guess the idea is if the individual logic LUT can run at 100 MHz, then if the clock of the system is no higher than 10 MHz, it will probably make timing on many / simple designs (< 10 LUT logic levels)

I also see that MACHX03 in QFP is unobtanium.

There would a use in the community for someone to put BGAs with bypass caps and a core regulator into a 100QFP 0.65mm  leadframe ? whattya think ? Not to make any money, I mean just to enable people to experiment a bit more .... Or a big DIL DIP

[ataradov]

For the internal logic, you don't need to guess or estimate. Even if you have 100 levels of logic, the tool just calculates the delay and limits the maximum clock for the FFs around the logic.  But this breaks apart quickly with multiple clocks in the design. Without ability to specify relative timing, things may get hairy. But I think for 1K LUT device, it is probably fine.

The bigger issue is the I/O pin timing. You just need to have very generous setup and hold times for anything to work.

Is there even technology to do that? Even just placing decoupling capacitors into the package increases the packaging cost a lot. I can't imagine placing a BGA IC and supporting components is cheap, if possible at all.

Single power supply versions of LCMXO2 are really easy to use already. Probably the least annoying FPGAs out there. And they are plenty powerful for experimentation. 

[nctnico]

There would a use in the community for someone to put BGAs with bypass caps and a core regulator into a 100QFP 0.65mm  leadframe ? whattya think ? Not to make any money, I mean just to enable people to experiment a bit more .... Or a big DIL DIP

A small PCB with castellated holes at the side (like uBlox and BLE / Wifi modules) is easier to make. Companies like JLCPCB can also take care of assembly.

[iMo]

..
1K LUT, 32K BRAM. configure from MCU SPI flash or Onboard OTP
..

1k Luts - too smallish today, imho. What you could try with it? PicoRV32_small @16-20MHz clock perhaps?

[ataradov]

Not everything needs an MCU. Sometimes you just need a real time reaction to events. The device is big enough to do motor control with necessary protections, for example.

[glenenglish]

I think Alex has the best option- LCMX02 is probably hobbyists best go-to option at the moment . I'v done a few professional  designs in recent times  using LCMX02s to solve things like
- high speed LVDS based large IO expander port serializer/deserializer, 
-PDM microphone x4 array  input to TDM PCM output (digital cic filters, multiplexing)  etc.

------ all good applications for FPGAs,  not easy nor practical applications for microcontrollers - where timing must be cycle correct for every I/O down to 15nS ......

I'll have to ask JLC what their minimum reasonable castellated hole size is. YEARS ago, I built some large PLCC modules by buying leadfreame-packaging and the fingers were thermosonically bonded down onto a small PCB.

[slburris]

At LCSC: https://www.lcsc.com/product-detail/Programmable-Logic-Device-CPLDs-FPGAs_Lattice-LCMXO2-1200HC-4TG144C_C1521637.html

I order a lot from them, so I'll probably just toss 10 or 20 of them into my next order of other parts.

Well, I ended up ordering about $300 of LCMXO2 in various sizes (100 and 144 pin packages), just to have parts in stock for projects.  That should keep me going for a year or so for "low cost" FPGAs until something better comes along.