Renesas "lowest cost" ForgeFPGA low-density FPGA - free eval boards

[mikeselectricstuff]

Apply for free  eval board : https://www.my-boardclub.com/boards/slg7evbforge/

1K LUT, 32K BRAM. configure from MCU SPI flash or Onboard OTP
50MHz +/-5% onboard osc + PLL
I/O only goes up to 2.75v
0.4mm QFN package

Datasheet
https://www.renesas.com/us/en/document/dst/slg47910-datasheet?r=25546631

[ftg]

Applied for one. Time will tell if I'm deemed worthy of one.

The 2.75v MAX IO's do sound a bit limiting.
Are there even that many <3V3 PMOD's out there?

[ataradov]

The I/O voltage limit is new. I guess they ran into some issues with the higher voltages and decided to not change the design. This combined with the need for 1.1 V core voltage regulator makes the device pretty pointless.

So, this is what they were working on for 3 years since the announcement?


So, it looks like it is entirely new design with the same name. Specs from the preliminary datasheet from 2 years ago:

Dense Logic Array
 Equivalent to 900 4-bit LUTs
 1.8 k DFFs
 5 kb distributed memory
 32 kb BRAM
 Configurable through NVM and/or SPI interface
 50 MHz High-frequency Oscillator
 3.41 MHz Low-power mode
 Phase-locked Loop (PLL)
 Input from external source or internal 50 MHz oscillator
 Power Supply
 VDDIO: 1.71 V to 3.6 V
 VDDC: 1.1 V ± 10%
 Power-On-Reset (POR)
 Available Package
 24-pin QFN: 3.0 mm x 3.0 mm, 0.4 mm pitch
 20-pin WLCSP: 1.85 mm x 1.64 mm, 0.35 mm pitch

New specs:

Dense Array of Configurable Logic
1120 5-bit LUTs
1120 DFFs
5 kb distributed memory
32 kb BRAM
Configurable through NVM and/or SPI interface
50 MHz On-chip Oscillator
Phase-Locked Loop (PLL)
Input from external source or internal On-Chip Oscillator
Power Supply
VDDIO: 1.71 V to 2.75 V
VDDC: 1.1 V ±5%
Power-On-Reset (POR)
GPIO Count
 19 GPIOs
Available Package
24-pin STQFN: 3.0 mm x 3.0 mm x 0.55 mm, 0.4 mm pitch

[glenenglish]

maybe they have some big customer they needed this part for, and just bought some IP and fabbed it. Maybe they have some internal kit (say an ADAS system) that they found they needed some glue logic for, and again, bought some IP and fabbed it.

amusing

[ataradov]

I think they did license the FPGA fabric. I don't remember their name, but there is some company that makes small FPGA IP.

But the rest of the design is theirs. At some point they admitted that the initial delays were caused by some issues with the early silicon and they needed a silicon revision. So, I guess the revision did not work out.

This voltage lowering is not intentional, since early engineering samples and boards they sent out used 3.3 V supply.


The whole thing is strange from the beginning. And in that time a lot more low end FPGAs became available. The only thing Renesas had is easy and lightweight IDE that did not need registration or licenses to use. But that only gets you so far if the silicon is crap.

[glenenglish]

yeah, agreed

as such,  I think it is for some internal glue logic they need for some product, and , hey, why not flog it on the market, see if anyone buys it. LOL..... If you want a tiny FPGA, u buy Lattice or Microchip.... 

[SiliconWizard]

We'll see still what they bring, for instance in terms of power consumption. Nothing wrong with having more alternatives. Whether it's good strategy for Renesas is another question, time will tell.

[tom66]

2.7V IO kills it for so many applications. Ok your FPGA is 3x3mm but if I need to pepper the IO in level translation ICs then it's not really that small is it?

Very weird that they'd release silicon like this with a known limitation that is so critical.

[mikeselectricstuff]

2.7V IO kills it for so many applications. Ok your FPGA is 3x3mm but if I need to pepper the IO in level translation ICs then it's not really that small is it?

Very weird that they'd release silicon like this with a known limitation that is so critical.

They probably have some big customers for whom that's not an issue. Wouldn't surprise me if this gets "fixed" in future.

[coppice]

2.7V IO kills it for so many applications. Ok your FPGA is 3x3mm but if I need to pepper the IO in level translation ICs then it's not really that small is it?

Very weird that they'd release silicon like this with a known limitation that is so critical.

Don't be so parochial. There are vast numbers of systems running on <2.7V these days. No part suits everyone. You just need to suit a substantial market to succeed. 2.7V would be an odd initial target voltage right now, but if you fail to achieve your goal while having a solid solution that suits substantial markets you need to get to market and start getting some revenue. You learn so much from the feedback you get with early parts in a family. That can really improve your follow ons.... assuming you are good at listening.

[asmi]

2.7V IO kills it for so many applications. Ok your FPGA is 3x3mm but if I need to pepper the IO in level translation ICs then it's not really that small is it?

Very weird that they'd release silicon like this with a known limitation that is so critical.

I disagree that it's critical, or even especially important. A lot of peripherals nowadays can work just fine at 1.8 V level or even lower, that's clearly where industry is heading to save power and/or reach higher performance for the same power, heck Xilinx FPGAs had 1.8 V only IO banks in Kintex-7/Virtex-7 for a long time now, and I didn't see many complaints about that. I for one always choose 1.8 V level for peripherals over 3.3 V versions whenever possible because it's got some serious upsides and almost no downsides. 3.3 V IO gets in the way of utilizing finer silicon nodes, and as they become more affordable, more and more devices will ditch 3.3 V IO for many advantages offered by finer nodes.

[PartialDischarge]

A problem with Renesas is that they tend to discontinue ICs pretty soon. Don't know if they make things for telecom, cars or whatever and when the big market disappears their parts do too.

[ataradov]

more and more devices will ditch 3.3 V IO for many advantages offered by finer nodes.

The core already works at 1.1 V and takes advantages of any new technology.  The fact that you need beefier transistors on I/O cells should not be a huge issue.

3.3 V would still remain relevant for a long time. But it is not even the issue here. Clearly they intended this to run at 3.3 V, but then could not figure it out after a couple mask changes, and then just gave up and released this half-baked device as is. Does not instill a lot of confidence.

[glenenglish]

All my FPGA designs are all 1.8V I/O. I have not used 3.3V on an FPGA for years....
Still use 3.3V with microcontrollers, and I have  TXU0101    1V-5V <>1V-5V  sc70 translators on tape and reel....

[asmi]

The fact that you need beefier transistors on I/O cells should not be a huge issue.

Of course it is an issue, because space on finer process nodes gets progressively more expensive, and at some point space taken by these IO cells might become a significant portion of the entire design, which kind of defeats the purpose of using finer node in the first place.

3.3 V would still remain relevant for a long time. But it is not even the issue here. Clearly they intended this to run at 3.3 V, but then could not figure it out after a couple mask changes, and then just gave up and released this half-baked device as is. Does not instill a lot of confidence.

That doesn't make any sense. There is nothing to figure out, you simply use the correct primitive from the tech library for the process that is provided by the fab, and you're done. If that primitive ends up not meeting specs, that's a fab's problem, not customer's.

[asmi]

All my FPGA designs are all 1.8V I/O. I have not used 3.3V on an FPGA for years....

That's the direction my designs are heading too. On my latest board I only had one IO bank powered by 3.3 V, and the main reason was that I wanted to use native TMDS support which requires 3.3 V Vccio.

[langwadt]

All my FPGA designs are all 1.8V I/O. I have not used 3.3V on an FPGA for years....

That's the direction my designs are heading too. On my latest board I only had one IO bank powered by 3.3 V, and the main reason was that I wanted to use native TMDS support which requires 3.3 V Vccio.

I found an interesting feature on a Xilinx FPGA. While you can use 3.3V powered bank for LVDS input you cannot use it for LVDS output, once the IO voltage goes above ~2.9V the LVDS outputs gets powered off to protect them

[asmi]

I found an interesting feature on a Xilinx FPGA. While you can use 3.3V powered bank for LVDS input you cannot use it for LVDS output, once the IO voltage goes above ~2.9V the LVDS outputs gets powered off to protect them

Yep, this is described in documentation - you can use LVDS receiver in bank with any Vccio (not just 3.3 V) provided that you don't use on-chip termination (and instead have external 100 Ohm termination resistor). MIG uses this trick for placing a system differential clock input in the same IO bank as regular memory IO pins.

[glenenglish]

I run  single 1.8V for VCCIO and VCCBRAM, AUX etc everything for most 16nm/28nm FPGA like xilinx, efinix etc

This means I have only two power planes to deal with  Vddcore and 1.8V.. IE no 3.3V. Those go in the upper 4 layers (TOP, Vcore, GND, Vio ) and I dont need any caps on the bottom side...nor does the fpga have to reach down below the FR4 core to the bottom 4 layers for power....

On 7 series though, 2.5V LVDS output, yes, need the extra small platelette. You can run them down to about 2.35V and they still make spec at full gas over temp. datasheet says 2.375V. It is worth it because you can save  quite a bit of heat.
1.8V LVDS compared ot 2.5 in xilinx is about 1/3 the power from memory......

anyway, yeah Renases , bit of a mystery there. It's an interesting year for FPGA because you have Lattice AVANT E, Altera Agilex5, and new SERDES RISCV hardcore Efinix all being production available by year end.
new Xilinx Spartan 8 is interesting for some (lots of 3.3V IO) but lacks 1.8V IO (quantity) for me.

[langwadt]

I found an interesting feature on a Xilinx FPGA. While you can use 3.3V powered bank for LVDS input you cannot use it for LVDS output, once the IO voltage goes above ~2.9V the LVDS outputs gets powered off to protect them

Yep, this is described in documentation - you can use LVDS receiver in bank with any Vccio (not just 3.3 V) provided that you don't use on-chip termination (and instead have external 100 Ohm termination resistor). MIG uses this trick for placing a system differential clock input in the same IO bank as regular memory IO pins.

it was quite few years ago, I'm quite sure it wasn't in the datasheet at that point

[asmi]

it was quite few years ago, I'm quite sure it wasn't in the datasheet at that point

Iit's been there for at least as long as I've been using these devices - so about 7 years:

• Differential inputs for these standards [LVDS, LVDS_25, MINI_LVDS_25, PPDS_25 and RSDS_25] can be placed in banks with VCCO levels that are different from the required level for outputs. There are some important criteria that need to be considered:
  
  • The optional internal differential termination is not used (DIFF_TERM = FALSE, which is the default value) unless the VCCO voltage is at the level required for outputs.
  • The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific device family data sheet.
  • The differential signals at the input pins meet the VIDIFF and VICM requirements in the corresponding LVDS or LVDS_25 DC Specifications tables in the specific device family data sheet. In some cases, to accomplish this it might be necessary to provide an external circuit to both AC-couple and DC-bias the pins.
• If the voltage exceeds 2.85V, the outputs will be in a high-Z state. The device should always be operated within the recommended operating range as specified in the 7 series FPGA data sheets.

[asmi]

I run  single 1.8V for VCCIO and VCCBRAM, AUX etc everything for most 16nm/28nm FPGA like xilinx, efinix etc

This means I have only two power planes to deal with  Vddcore and 1.8V.. IE no 3.3V. Those go in the upper 4 layers (TOP, Vcore, GND, Vio ) and I dont need any caps on the bottom side...nor does the fpga have to reach down below the FR4 core to the bottom 4 layers for power....

Pretty much all of my boards contain DDR3 interface, so I still need at least 1.35/1.5 V rail as well, in addition to 1.0 and 1.8 V rails.

new Xilinx Spartan 8 is interesting for some (lots of 3.3V IO) but lacks 1.8V IO (quantity) for me.

Do you mean Spartan UltraScale+? If so, HDIO pins support 1.8 V standards among other. - though they are MUCH slower than good old HR ones. Also higher-spec devices will have dedicated pins for hard LPDDR5 controllers, so  you won't have to spend HP pins on memory interfaces anymore (typical deal with HP banks in previous device families), and can use them for something else for a change.

[glenenglish]

yeah, they're HDIO. good for SPI etc...
and the rest are XPIO, the 1.2V logic, but they are mostly MIPI banks

I use LPDDR2(Zynq)  or DDR4 (MPSoc)  so I only need 1.2V extra....

   or HyperRAM ( non SoC) , cant remember but the HDIO are probably OK for HyperRAM... lets see -

HDIO - pseudo diff output. true diff input  but they do have IODLY blocks
https://docs.amd.com/r/en-US/ug571-ultrascale-selectio/Introduction-to-High-Density-I/O-Banks
On Versal they're 250 Mbps DDR. mmm  not good enough for full speed hyperram. ah well. but good for motor controllers etc, right ?

So 3.3V is clearly not dead, probably alot of automotive people wanting it

[langwadt]

it was quite few years ago, I'm quite sure it wasn't in the datasheet at that point

Iit's been there for at least as long as I've been using these devices - so about 7 years:

• Differential inputs for these standards [LVDS, LVDS_25, MINI_LVDS_25, PPDS_25 and RSDS_25] can be placed in banks with VCCO levels that are different from the required level for outputs. There are some important criteria that need to be considered:
  
  • The optional internal differential termination is not used (DIFF_TERM = FALSE, which is the default value) unless the VCCO voltage is at the level required for outputs.
  • The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific device family data sheet.
  • The differential signals at the input pins meet the VIDIFF and VICM requirements in the corresponding LVDS or LVDS_25 DC Specifications tables in the specific device family data sheet. In some cases, to accomplish this it might be necessary to provide an external circuit to both AC-couple and DC-bias the pins.
• If the voltage exceeds 2.85V, the outputs will be in a high-Z state. The device should always be operated within the recommended operating range as specified in the 7 series FPGA data sheets.

checked thee revision notes for https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO

05/15/2015 ,  Added note 2 to Table 1-55

[asmi]

checked thee revision notes for https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO

05/15/2015 ,  Added note 2 to Table 1-55

Note 1 and additional narrative in "LVDS and LVDS_25 (Low Voltage Differential Signaling)" section (towards the bottom of the page 92 in current revision 1.10) has been added back in 2012. There is even a schematics added on how to AC-couple and DC-bias receiver in case incoming LVDS has different common voltage. So it's there for at least 12 years, which is why I thought it's been always there.