verilator width warnings

[promach]

Could anyone advise about the verilator width warnings below ?

verilator -Wall --lint-only in_buf_load.v
%Warning-WIDTH: in_buf_load.v:35: Operator ADD expects 12 bits on the LHS, but LHS's VARREF 'idx_n' generates 9 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: in_buf_load.v:35: Operator ADD expects 12 bits on the RHS, but RHS's VARREF 'idx_k' generates 9 bits.
%Warning-WIDTH: in_buf_load.v:35: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's ADD generates 12 bits.
%Warning-WIDTH: in_buf_load.v:51: Operator LT expects 32 or 3 bits on the LHS, but LHS's VARREF 'index_i' generates 2 bits.
%Warning-WIDTH: in_buf_load.v:73: Operator ADD expects 32 or 12 bits on the LHS, but LHS's SEL generates 8 bits.
%Warning-WIDTH: in_buf_load.v:73: Operator ADD expects 32 or 12 bits on the RHS, but RHS's VARREF 'index_j' generates 4 bits.
%Warning-WIDTH: in_buf_load.v:88: Operator ADD expects 32 or 9 bits on the RHS, but RHS's VARREF 'index_k' generates 4 bits.
%Error: Exiting due to 7 warning(s)
%Error: Command Failed /usr/bin/verilator_bin -Wall --lint-only in_buf_load.v

Code: [Select]

module in_buf_load(clk, reset, buf_address); // generates DDR address for the AWS guy code

localparam MAX_J = 10;
localparam MAX_K = 10;
localparam GIGA = (1 << 9); // 10^9
localparam BITS_PER_BYTE = 8;
localparam NUM_OF_BITS_IN_TWO_GIGABYTE = (GIGA << 1)*BITS_PER_BYTE;

parameter BUFFER_WIDTH = 16;
parameter DATA_WIDTH = 4*BUFFER_WIDTH; // ap_uint<64> *i_data which contains 4 different 16-bit data

// 2 Gigabyte of data, each contiguous chunk of data is 64-bit
parameter NUM_OF_DATA_ENTRIES = NUM_OF_BITS_IN_TWO_GIGABYTE/DATA_WIDTH;

parameter N = 4; // number of input feature maps
parameter n = 1; // input feature map index (just to identify map)
parameter Tn = 4; // number of tiles for input feature maps (divide and conquer due to resource limits)
parameter r = 256; // FEATURE_SIZE_WIDTH
parameter c = 256; // FEATURE_SIZE_HEIGHT

parameter IDX_N_WIDTH = ($clog2(N*100));
parameter IDX_R_WIDTH = ($clog2((r+MAX_J)*10));
parameter IDX_K_WIDTH = ($clog2(c+MAX_K));

parameter Tn_WIDTH = $clog2(Tn);
parameter r_WIDTH = $clog2(r);

input clk, reset;
output [$clog2(NUM_OF_DATA_ENTRIES)-1:0] buf_address;

//wire signed [DATA_WIDTH-1:0] local_i_buf [N-1:0][MAX_J-1:0][MAX_K-1:0];

//assign local_i_buf = ;

assign buf_address = idx_n + idx_r + idx_k;

// used for generating address indexes

reg [IDX_N_WIDTH-1:0] idx_n;
reg [IDX_R_WIDTH-1:0] idx_r;
reg [IDX_K_WIDTH-1:0] idx_k;

reg [$clog2(N)-1:0] index_i;
reg [$clog2(10)-1:0] index_j;
reg [$clog2(10)-1:0] index_k;

always @(posedge clk)
begin
if(reset) index_i <= n;

else if(index_i < N) index_i <= index_i + Tn[0 +: Tn_WIDTH];
end

always @(posedge clk)
begin
if(reset) idx_n <= n*100;

else idx_n <= index_i * 100;
end


always @(posedge clk)
begin
if(reset) index_j <= 0;

else if(index_j < 10) index_j <= index_j + 1;
end

always @(posedge clk)
begin
if(reset) idx_r <= (r + 0) * 10;

else idx_r <= (r[0 +: r_WIDTH] + index_j) * 10;
end


always @(posedge clk)
begin
if(reset) index_k <= 0;

else if(index_k < 10) index_k <= index_k + 1;
end

always @(posedge clk)
begin
if(reset) idx_k <= c + 0;

else idx_k <= c + index_k;
end


`ifdef FORMAL

initial assert(reset);

reg first_clock_had_passed = 0;

always @(posedge clk) first_clock_had_passed <= 1;

always @(posedge clk) if(first_clock_had_passed) cover($past(reset) && buf_address != 0);

`endif

endmodule


[BrianHG]

have you tried designating the exact bits at each step forcing the matter?
eg:

Code: [Select]

warning line:

assign buf_address = idx_n + idx_r + idx_k;

to:

assign buf_address[$clog2(NUM_OF_DATA_ENTRIES)-1:0] = idx_n[IDX_N_WIDTH-1:0] + idx_r[IDX_R_WIDTH-1:0] + idx_k[IDX_K_WIDTH-1:0];

similar on line 51:
else if(index_i[$clog2(N)-1:0] < N[$clog2(N)-1:0]) index_i <= index_i + Tn[0 +: Tn_WIDTH];

Though this one may cause problems as if 'N" has more bits than [$clog2(N)-1:0].  You may also try:
else if(index_i[$clog2(N)-1:0] < N[2:0]) index_i <= index_i + Tn[0 +: Tn_WIDTH];

Assuming N is never greater than 7, however, you compiler seems to be saying that [$clog2(N)-1:0] for index_i is only = to [1:0], ie 2 bits and N being =4 is 3 bits.
When comparing different number of bits together, some compilers want you to be explicit knowing that the < 'LT' will always hold true.

Since I'm not decoding this code, I can tell you some of these warnings are important like the one with the second one I highlighted.  There is no way index_i can be > or = 'N' since it is only 2 bits while 'N=4' is 3 bits already...

[promach]

Code: [Select]

assign buf_address[$clog2(NUM_OF_DATA_ENTRIES)-1:0] = idx_n[IDX_N_WIDTH-1:0] + idx_r[IDX_R_WIDTH-1:0] + idx_k[IDX_K_WIDTH-1:0];
No, this does not help. Same exact error

[BrianHG]

Your compiler is telling you that the size of your 'buf_address[$clog2(NUM_OF_DATA_ENTRIES)-1:0]' on the left hand side of the '=' in it's number of bits is too small for the total sum of the equation on the right hand side.  It needs to be larger in bits, or information is lost.

[promach]

Code: [Select]

localparam GIGA = (1 << 119);

I changed the buf_address bitwidth length, yet still width warnings

[BrianHG]

What is the value of ' $clog2(NUM_OF_DATA_ENTRIES)-1 ' ?

[promach]

Code: [Select]

localparam GIGA = (1 << 9); // 10^9
localparam BITS_PER_BYTE = 8;
localparam NUM_OF_BITS_IN_TWO_GIGABYTE = (GIGA << 1)*BITS_PER_BYTE;

parameter BUFFER_WIDTH = 16;
parameter DATA_WIDTH = 4*BUFFER_WIDTH; // ap_uint<64> *i_data which contains 4 different 16-bit data

// 2 Gigabyte of data, each contiguous chunk of data is 64-bit
parameter NUM_OF_DATA_ENTRIES = NUM_OF_BITS_IN_TWO_GIGABYTE/DATA_WIDTH;

[BrianHG]

What is the value of ' $clog2(NUM_OF_DATA_ENTRIES)-1 ' ?

Give me the actual number...
$clog2(NUM_OF_DATA_ENTRIES)-1
Solve the equation...