Protecting against bus contention in prototype

[ivan747]

Hi everyone,

I want to embark on a project that wil conenct an FPGA to a device parallel bidirectional bus. The bus is not clearly documented, so I am not 100% sure when the device will output data on the bus. I want to protect both the FPGA dev board and the device because they cost some money.

I think resistors in series on every line is a good solution, but I don't know what value should I choose. The bus is 3.3V and its clock runs at up to 17MHz. Single data rate. I will have a ribbon cable (at least 20cm for ergonomics). So signal integrity is a factor, I think.

If I go with a value that limits the current below the FPGA's rating, say 3.3mA, the resistance is 1kohm. Empirically I think that's too high of an impedance considering the ribbon cable. If I go with something like 100ohm, empirically I think it can drive the ribbon cable but I don't know if the FPGA can survive that.

Is there a magical solution?

[ataradov]

Use bus transceiver ICs between the devices. Consider them to be disposable, but generally they are more robust and 100 Ohm current limiting is sufficient.

[xvr]

Get the minimum of maximum load current of FPGA output and maximul load current of target device. Then divide logic high voltage to this current. You will get resistors value.

Example: 20mA of max current, 3.3V of logic 1 give 165R

[BrianHG]

I use 74xx245 on my PCB, with optional resistor packs beneath the 245 buffers so I may use either / or just  by mounting the 245 or 2x 4sip parallel resistor packs since the 8 bit bus comes in and out in parallel on each side of the 245.