Generally in a VHDL process, all updates to signals happen only when process ends. So you can "change your mind" several times in a process and the last decision will remain effective. This also means that you always see the value of the signal which it had before the process started, even after you changed it (on the same execution).
That means that your TMP signal will contain the value of cnt just before reset. Then cnt will be reset. This also means that cnt signal is an inferred latch, which is generally a bad idea on a FPGA. You should try to implement this synchronously, like suggested.
Also note that reset signal will usually need to obey some timing constraints (recovery/removal) for the implementation to work reliably. So even if reset is "asynchronous", it still usually needs to be synchronized with the clock.
Regards,
Janne