I've often thought about using a pogo-pin connector instead of having to find room for a physical connector on the board, so would be happy to give this a try. Do you have any links to suitable products?
I've bought mine here:
www.tag-connect.com For you I would recommend to get a 10 pin legged cable + adapter for Xilinx programmer:
https://www.tag-connect.com/debugger-cable-selection-installation-instructions/xilinx-platform-cable-usb#85_171_146:~:text=Xilinx%202mm%20to%2010%20Pin%20Plug%2Dof%2DNails%E2%84%A2%20%2D%20With%20Legs specifically, "Xilinx 2mm to 10 Pin Plug-of-Nails™ - With Legs". BTW some of these things are carried by the likes of Digikey, so you might want to check if they got some in stock locally, because shipping from that company directly from US will probably cost you more than from DK et al which tend to have local warehouses. Just make sure you double check parts numbers you are ordering - this company has got a ton of adapters for different programmers/debuggers, so it's easy to order a wrong one by mistake.
That reduces the cost to something more reasonable. I'll see if I can get some samples. 
If my experience is anything to go by, you should have no problems. At no time did they ever asked me a million of questions which other companies typically ask (like your project, volume, dates, etc.) - they just shipped what I asked for with no fuss (and even paid for express shipping from US!), which made me a loyal customer of theirs (and an easy recommendation for others) because I know I can rely on them for both samples and for actual productions parts should the likes of DK decide for some reason to not stock the part I'm after. Of course I don't abuse this service by requesting all their inventory or anything like that, but I tried requesting samples from one of their competitors, which asked me to fill out a 3 screens-long form with a metric ton of questions, to which I just said "screw it" and bought samples myself because my time and sanity are worth more to me than these samples were.
I haven't heard anything yet, so will keep patiently waiting.
Check your order status on their website. They never sent me a shipping notification, though later in a day DHL has sent me a request to pay sales tax and their customs fee.
I've never used them before, but it looks like I'm going to need to design for differential clocks rather than single-ended ones for extra stability, especially with the DDR3 controller. How many clocks do I need for the FPGA? I've run through Vivado earlier and created a DDR3 controller using MIG (for the first time ever - details below) - it's talking about a dedicated clock for the DDR3?
There are many ways to skin this cat. I often used a single-ended 100 MHz base clock and a PLL to generate both clocks required for MIG. But this kind of "wastes" one extra MCMM because MIG itself uses MCMM. In this case you select the frequency for that clock to something like 200 MHz and select a "no buffer" option in the MIG.
Alternative often used solution is to use 200 MHz LVDS differential clock selected right in the MIG and select a "Use system clock" option for the reference clock (I will explain below what it's for). The advantage of this approach is that you only use a single MCMM.
So, I've run MIG to make a start on setting up a DDR3 controller simulation; these are the settings I used:
Is that right or have I made any mistakes? I wasn't sure about the bank choices - it was defaulting to assigning the controls/address/data to Banks 14-16, but that's no good as it's sharing with the configuration pins, so I've moved all the DDR3-related IO to Banks 34 & 35.
See, it wasn't that bad, was it?
Like I said above, I would select "5000 ps (200 MHz)" in the "Input Clock Period" drop down, on the next page System Clock: "Differential" (or "No Buffer" if you want more flexibility on which pin(s) your system clock will be), Reference Clock: "Use System Clock" (this option will only appear if you set your input clock period to 200 MHz).
As for pinout, I would do it like this:
Bank: 34
Byte Group T0: DQ[0-7]
Byte Group T1: DQ[8-15]
Byte Group T2: DQ[16-23]
Byte Group T3: DQ[24-31]
Bank: 35
Byte Group T1: Address/Ctrl-2
Byte Group T2: Address/Ctrl-1
Byte Group T3: Address/Ctrl-0But it's just a preliminary pinout to give you some high-level idea, once you actually have a layout, you would go "Fixed Pin Out" route in the wizard and specify each pin assignment explicitly.
As mentioned above, not sure about reference_clock and system_clock. I presume system_clock is the main FPGA clock, which could be running at a different frequency to the DDR3? Is the reference clock supposed to be 400MHz or 1/4 of the system_clock?
System Clock is the one which will be used to derive the actual memory interface clock, while Reference Clock is used to drive special hardware block - "Delay Controller", which is used by delay blocks as time reference, that clock has to have a fixed frequency of 200 Mhz (in some cases and for some devices it can also be 300 or 400 Mhz). MIG outputs ui_clk, which is the one your HDL has to use to interact with the controller, it is either 1/2 or 1/4 of a memory frequency.
Home
Help
Search
Login
Register
