Oh? I figured following an existing working schematic, I couldn't go too far wrong.
It's not that simple with FPGAs because pinout is partly driven by the kind of I/O logic you want to implement. Not to mention a lot of Chinese boards suffer from many issues like underpowered PDS and bad thermal design, and I don't want you accidentally "importing" those problems into your boards.
I'm installing Vivado via the unified installer as we speak. Just hoping the simulation side of things isn't too different from what I've been using - I really need to get a grip of simulation. ![Shocked :o](https://www.eevblog.com/forum/Smileys/default/shocked.gif)
If anything, it's more simple in Vivado, because it has a separation between "real" hardware HDL and simulation-only stuff, plus the simulator is integrated into IDE itself, while it still officially supports using external simulators if you choose to do so.
I know, I can be a little hot-headed and want to rush in to the fun stuff.
Thankfully you guys are here to reign me in a little!
No worries, I'm more like you, which is why I've wasted a ton of money on dud PCBs due to stupid mistakes because "I just wanna build it already!!!" mentality
![Banging Head |O](https://www.eevblog.com/forum/Smileys/default/bangheadonwall.gif)
You wouldn't believe how many times I found errors in my PCBs right after I sent it out to manufacturing and it was too late to change/cancel the order so I was waiting for boards
knowing they are duds! That's why I've introduced some house rules for myself to slow things down, and recommend others to do the same. Delay of one day before your place an order is not going to matter to a hobbyist, but it often mean a ton because you can discover some problems with your PCB when you open it up on the next day with a fresh mind. And since we're now working with pricey stuff, taking it easy might just mean having one less revision of a PCB and saving you in the best case some of face palming once you discover the problem, or in the worst case some fireworks and smoke from expensive components. As you climb up the complexity ladder, the stuff you work with becomes progressively more expensive, so it's good to learn good habits from the get-go, or it can literally cost you quite a bit of money.
Good point. My inexperience showing through again, not really understanding the relative speeds of all these different protocols. To me though, DDR3 is a black box and although I tried routing to a PSRAM (I think it was) aaaages ago, I needed your help in finishing that. And that's nowhere near as complex as this project will be. I have the vaguest understanding of trace impedance and impedance-matching from the very limited work I've done with USB on these various projects, but on the scale of a 32-bit bus on a 6- (or more!) layer board... ![Scared :scared:](https://www.eevblog.com/forum/Smileys/default/scared.gif)
That complexity is very overblown. All of that impedance stuff comes down to setting up a specific trace widths and spacings, so once you calculate the widths (it's usually different for different signal layers) you only need to remember to set it for any trace you are routing, and that's it. Routing DDR is a lot like playing chess - you need to think ahead in order to not route yourself into a corner, so as you route a trace, you need to think about how you can route it in a such a way as to be able to also route adjacent traces. I actually like it exactly because how methodical it is.
As for 6 or more layers - you seem to think that having more layers makes routing harder, but in reality it makes it
easier because you have more signal layers and so more possibilities of how to route your signals! And the more layers you have, the easier it is to route! This is why nowadays I do 4 layer boards even for simple designs - because my time is worth more than the cost differential between manufacturing a 2 layer and a 4 layer PCB.
Okay, well I can't think what I would use GTPs for, so not including them on the core board would remove the need for two additional power supplies and free up the PCB real-estate they would otherwise consume. The downside is that the core board wouldn't have GTPs and there'd be no option for their use on a carrier board as a result. If I include them on the core board, I don't have to populate the power supplies or use them on the carrier board I suppose, but someone else might want to, so I really should include them I guess. ![Smiley :)](https://www.eevblog.com/forum/Smileys/default/smiley.gif)
Oh, I thought I already gave you some examples. Here are some I can think of right off top of my head:
1. Want to have access to a hard drive? No problem - you can implement a SATA interface using GTP and access any SATA HDD or SSD.
2. Want to work with something even faster and physically smaller? No problemo, you can implement an M.2 port and connect NVMe SSD to it.
3. Maybe you want to add ability to output something more modern than 1080p@60 - like 1080p@120, or 1440p@144, or even 2160p@120 (that's 4K resolution)? Again, GTPs come to a rescue - both HDMI 2.0 and DisplayPort 1.4 can be implemented (you will need some external circuitry for HDMI 2.0, but that's not the point).
4. Eventually you are going to run out of logic inside A100T (and you only need to look at what you already went through to see that it's bound to happen as some point). So you will need to somehow split your logic among two (three, four, ...) FPGAs. But how do you connect them to give you a high-bandwidth link such that this interconnect won't hinder your design? How about having to route just four differential traces and having almost as much bandwidth as your existing 16 bit wide DDR3 interface has? Or even going all way in and implementing a PCI Express root port with a bunch of PCI Express slots where you can plug in other FPGA boards, or even some off-the-shelf cards like USB 3 interface adapter? GTPs make all of that possible.
That list can go on and on. 2.5G Ethernet? Sure! Fiber connection? Here you go! 4 1G Ethernet ports using just one pair of differential traces (QSGMII)? Again, not a problem! So, yeah, unless you are really in a pickle, not routing out GTPs is a biiig mistake in my opinion. It doesn't mean you have to use them right away - hence my suggestion for module/baseboard split. Respining or even redesigning baseboard is likely going to be much cheaper than respining the whole FPGA board.
Yeah, my HDL skills aren't great, though they've come on leaps and bounds since I first learned about FPGAs... The CPU is on the list for an upgrade. Even the limited work I've been able to do on software for the uCOM is highlighting some annoying limitations with the Z80, I have been outlining plans for a 68020 version, but that's a long way off yet. Maybe I should stretch the design to an 030 or 040 clocked at 50MHz or more..
Vivado ships with a free Microblaze CPU (which is heavily inspured by MIPS microarchitecture), together with a software toolchain (Vitis), source code-level line-by-line debugging and everything else you expect to have in a modern software development IDE. And it can be configured so that it can run Linux. Also it's quite small (in terms of resources) so you can even put multiple of them to make a multi-core design.
Of course nothing prevents you from using any other CPU cores. As long as you have full HDL code for it, you can just plug it in.
I'm looking at using these for the power supplies instead: TPS62823.
Be careful with TI parts, as someone who preferentially used their parts in the past I can tell you that their inventory is VERY sketchy nowadays. Soldering LGA modules is not a problem, no x-ray is required unless you plan to do a mass production, a hot air gun is all that required. And since a lot of these modules are designed to work at very high temperature (125°C is not uncommon), you need to try really hard to burn them down with a hot air gun, especially if you use leaded solder.
Yeah, I'm definitely somewhere between anger and depression with KiCAD at the moment. Wait 'til I start using Vivado!
Yeah okay, I'm feeling the pro-KiCAD vibe here and will endeavour to put some more effort into understanding and using it. You're all making a very good argument for it.
You know, EasyEDA is free as well, and makes ordering the PCBs as easy as a couple of clicks of the mouse, no messing around with BOMs and all the other complexity KiCAD has. ![Confused :-//](https://www.eevblog.com/forum/Smileys/default/confused0024.gif)
My problem with EasyEDA is that it's web-based, and consequently slow. I still remember how painful it was to route like 10 traces, now I shudder to think what it's gonna be like routing close to a hundred of them! KiCAD on the other hand is a desktop application, and so it can take advantage of the GPU to do the heavy lifting (ooh the irony of using a power of GPU to design a GPU!
![Grin ;D](https://www.eevblog.com/forum/Smileys/default/grin.gif)
), that's why it has no problems displaying very complex PCBs.
Also I'm not exactly sure how versioning works in EasyEDA, while KiCAD uses text-based files which can be managed by git for example.
There's something about a PCB layout that I find almost mesmerising. I hope I'm not the only one who can enjoy a good trace layout, especially if you've designed it yourself and know the problems you've faced getting that last trace to its destination. ![Azn ^-^](https://www.eevblog.com/forum/Smileys/default/azn.gif)
Don't worry - you will get it all with this design! There is going to be plenty of routing-tearing down cycles. Make sure you use a version control so that you can always go back to previous state - because you
will need to go back.