CPLD passthrough in ISE

[_pat_]

Hello All!

Please forgive me if this is obvious.... but....

Whilst trying to debug some hardware which uses a 9500XL series CPLD as (among other things) an address / CS decoder to allow a single SPI controller to access more devices than is inherently possible with a microcontroller on its own, a situation arose where I wanted to remove the address decoding and only ever drive one chip's select :

The combinatorial logic thus went from something like :

Code: [Select]

CS3 <= NOT ( (NOT A0) AND A1 AND (NOT CS) );

to simply :

Code: [Select]

CS3 <= CS;
This results in both the CS3 and CS pins on the device being unconnected and ISE complaining about LOC constraints for CS3. It seems to be identifying that, without any logic in the path, the two nets are the same and it seems to be deleting one of them during the optimisation, thus leaving them unconnected (but it is not treated as an error). Interposing "any" logic that cannot be optimised out does restore the connectivity. But despite trying various attributes I have yet to find any way to persuade ISE that it should take a signal directly from an IBUF to an OBUF.

I'm not sure if this is as one might expect or if it is incorrect behaviour by ISE. It might make much more sense with a non-top-level module, after all if the input and output signals are the same then why bother going through the module at all, why not just route the "output" through the fabric "directly" but for top level there is no higher level fabric to pick up the actual output.

Open to suggestions to persuade ISE to connect an IBUF to an OBUF rather than optimise a net away breaking connectivity.

Cheers,

Pat.