I'm not sure if this should go here or elsewhere, since it's only indirectly related to FPGAs, and rather about DRAM. I'm learning verilog and making a toy/hobby CPU. I'm looking to interface with some very old 414256 DRAM modules (datasheet is attached as pdf below) and I have 3 questions.
The first is, I'm confused as to the point of the #G pin. It's not shown in any of the timing diagrams (except for G-controlled late write cycle, and a few others) and yet it's mentioned in the descriptions of the timing diagrams. It seems strange that they would explicitly talk about #G and yet not show it.
The second question is about setup times. Both #RAS and #CAS have a setup time for the address (and other pins) of 0ns. So I'm assuming I can set the address (and #W) pins on the same clock as I transition #RAS or #CAS? I just sort of assumed that if the address was 'clocked in' to a register that the address would have to be setup some time before the #RAS or #CAS transition. Also, despite all signals being sent on the same clock cycle, due to tiny variations in delay, could there be issues? Am I overthinking or misunderstanding this?
The time between the #CAS transition and the time that the data is valid is measured as tCAC. Now I assume that doesn't include things like signal transmission over the pcb, and 'clocking in' the data to a register on the FPGA. If tCAC is say 25ns, do I have to wait 26ns? 27ns? before I can reliably read the data? Is there a way to estimate this delay?
Thanks in advance for your time and patience