Cyrite HDL 'official': Python HDL and verification

[laugensalm]

Hi,

I'm hereby announcing a somewhat stable release of a Docker container containing a comprehensive development ecosystem based on a Python HDL (named Cyrite HDL after some history).

The underlying generator kernel was originally designed to generate signal processing pipelines the 'pythonic way', or: poor man's HLS. It then took a little swing of additional experiments to emulate MyHDL while allowing to carry along VHDL and Verilog legacy. Now it's at a stage where it's safe to play with it.

The novel part: a dual execution context, basically meaning, that the same code notation is executed as native Python or transpiled to another representation (modular HDL, RTL). This opens up a new field of verification methods, which turned out efficient for modelling of complex algorithms. This might also answer some of question marks raised in this thread https://www.eevblog.com/forum/fpga/vunit-uvvm-osvvm-what-are-similarities-and-differences/

The howto/examples repo with Jupyter notebooks:

https://github.com/hackfin/cyrite.howto

Hitting the Binder button will launch a Jupyter Lab 'IDE' in your browser after a while. Behind it is the mentioned Docker container which you can also run at home.

Teasers:
- Procedural stuff: CRC, SoC register map decoders
- Pipelined vector operations
- ..and verification of the above by Co-Simulation via CXXRTL (fast!) or generation of HDL testbenches
- yosys, iverilog, ghdl included


Primarely released for free, educational use (industrial FPGA targets are mostly not referred to), I'd of course love to hear about it if someone comes up with an interesting verification method. And about bugs, irregularities you might come across, too.