Microchip announces PolarFireSOC FPGA with penta core RISC-V

[brucehoult]

Details: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga

Press gumpf: https://www.sifive.com/press/industrys-first-risc-v-soc-fpga-architecture-brings

[brucehoult]

Found the Microchip/MicroSemi press release now:

https://investor.microsemi.com/2018-12-04-Industrys-First-RISC-V-SoC-FPGA-Architecture-Brings-Real-Time-to-Linux-Giving-Developers-the-Freedom-to-Innovate-in-Low-Power-Secure-and-Reliable-Designs

[daqq]

Looks nice! It's nice to see someone stirring up the FPGA market.

[filssavi]

I will wait the pricing before saying anything about this product because is doesn’t look cheap

[brucehoult]

I will wait the pricing before saying anything about this product because is doesn’t look cheap

Yes. I have no idea on pricing. I *hope* it will be competitive with Zynq, but who knows?

They also don't seem to have said anything about MHz. The FU-540 coreplex runs at up to 1.5 GHz in 28nm on the HiFive Unleashed, but it may be quite different in an FPGA-compatible process.

I guess you could think of the HiFive Unleashed plus MicroSemi HiFive Unleashed Expansion board (which is based on a PolarFire FPGA) as a kind of prototype for this, but we're going to need to see prices a lot lower than the $1k plus $2k for that combination!

[brucehoult]

Looks like it's going to be a while before these are available.

"The Microsemi division of Microchip will describe a five-core complex that it will embed in its PolarFire FPGAs by early 2020. The chip marks its first step in a plan to standardize on use of RISC-V."

https://www.eetimes.com/document.asp?doc_id=1334032

[coppice]

I think we'll believe it when we see it, but its interesting to see even an early announcement of work in progress with a RISC-V core by one of the mainstream silicon vendors.

[JPortici]

i saw this announcement a couple of weeks ago.. didn't even know microchip got microsemi

PIC32RZ when?

[brucehoult]

I think we'll believe it when we see it, but its interesting to see even an early announcement of work in progress with a RISC-V core by one of the mainstream silicon vendors.

NXP also just announced a chip (RV32M1) with a Cortex M0+, an M4F, and two RISC-V cores from the PULP project at ETH Zurich: a Zero-RISCY paired with the M0+, and a RI5CY paired with the M4F. It also has a ton of peripherals including Bluetooth LE 5.0, USB 2.0, uSDHC, RTC, ADC, CRC/AES/DES/SHA/RSA/ECC accelerator.  https://github.com/open-isa-org/open-isa.org/blob/master/Reference%20Manual%20and%20Data%20Sheet/RV32M1DS_Rev.1.1.pdf

Plus there is a board with this chip that you can order for free (as far as I can tell NXP themselves are absorbing the cost), and they were giving away a lot of them today at the RISC-V Summit http://open-isa.org/order/

[JPortici]

http://open-isa.org/order/

US Only

[kfnight]

The cheapskate in me wants to pick one up. Who doesn't like free stuff? But I'm not sure what I'd use it for.

[westfw]

NXP also just announced a chip (RV32M1) ... a Zero-RISCY paired with the M0+, and a RI5CY paired with the M4F.

I don't quite understand what that is supposed to accomplish - aren't the ARM and RISCV CPUs sort-of similar in capabilities?  Why pair them together?

[coppice]

NXP also just announced a chip (RV32M1) ... a Zero-RISCY paired with the M0+, and a RI5CY paired with the M4F.

I don't quite understand what that is supposed to accomplish - aren't the ARM and RISCV CPUs sort-of similar in capabilities?  Why pair them together?

It sounds like a device just to test the waters, and gauge the reaction. Also, when some ideologue idiot says "does it us an ARM core" the honest answer is "yes".

[rstofer]

The cheapskate in me wants to pick one up. Who doesn't like free stuff? But I'm not sure what I'd use it for.

And what toolchain do I need for the FPGA and, say, C for the RISC-V?  Are the tools already available?

[PCB.Wiz]

I don't quite understand what that is supposed to accomplish - aren't the ARM and RISCV CPUs sort-of similar in capabilities?  Why pair them together?

 As mentioned above, this is marketing, plus a good way to keep ARM license fees honest
If NXP have a proven RISC-V in silicon, you can see how the next license negotiations will pan out. 

[brucehoult]

The cheapskate in me wants to pick one up. Who doesn't like free stuff? But I'm not sure what I'd use it for.

And what toolchain do I need for the FPGA and, say, C for the RISC-V?  Are the tools already available?

There has been RISC-V gcc and so forth for a few years already, and it all got upstreamed into standard binutils, gcc, glibc, newlib about a year ago, though improvements are still being made rapidly.

If you want the latest, and don't mind building things yourself (takes about 20 min on a quad core i7) then go to https://github.com/riscv/riscv-gnu-toolchain and follow the instructions.

There's also a lot of information at https://wiki.debian.org/RISC-V including instructions for getting pre-built toolchains.

Most recent distros should just be able to apt-get or yum or whatever by now.

[brucehoult]

There's some quite good information in this article

http://linuxgizmos.com/worlds-first-risc-v-based-fpga-soc-runs-linux/

[oPossum]

LTT @ SiFive HQ

[brucehoult]

Slightly off the thread, but Qualcomm announced today at the RISC-V Summit that they'll be shipping a "high performance" RISC-V device in 2019.

[ezalys]

I feel like higher end chips are named by spinning two big jeopardy style wheels with names on them. One says "Polar" "Cold" "Dragon" and the next "Fire", etc. "Dragonball" "Coldfire" "polarfire." Really cool.

[legacy]

And what toolchain do I need for the FPGA and, say, C for the RISC-V?  Are the tools already available?

No commercial tools, unfortunately. Only GNU GCC and LLVM.

[legacy]

If you want the latest, and don't mind building things yourself (takes about 20 min on a quad core i7) then go to https://github.com/riscv/riscv-gnu-toolchain and follow the instructions.

On DTB we have just created a special "catalyst" for this; on Host=HPPA2, Target=RISCV, where HPPA2=C8900,4cores@1.1Ghz, it took 6 days 24h/24 to build all this stuff from stage1 to stage4.

Given a bootstrapper (which is the real problem when you are not on x86 host), a GCC-toolchain can be (re)built in 1 day.


That's funny since our Arise-v2 HL compiler compiles and builds in just 10 minutes on the same machine. Ok, it's not a C compiler, and it's not GCC, but hey? 10 minutes makes people nice and very happy!

GCC is definitively a bloated amount of code, and GNU/BSD/whatever is used for the userland of our Linux and BSD systems is no different: excessively bloated due to the bad assumption that people have Ghz computing power, with hundreds of cores, and Terabyte of ram 

e.g. can't norm people assume that I need 64bit (>>4Gbyte)  for the stack just to compile a browser

[legacy]

Porting Ada to HPPA2 has recently been a bloody experience. I really hope Ada (GNAT) will go on RISCV with less suffering.

[Ice-Tea]

So... microsemi now belongs to microchip?

[SiliconWizard]

So... microsemi now belongs to microchip?

Indeed: https://www.microchip.com/investor/Pressrelease/MCHP%20to%20Acquire%20Microsemi%20Corporation.030118.pdf