AES 256 FPGA core

[Guy Shemesh]

Hi

I need a recommendation free AES256 FPGA core - for a project involving software and hardware co-processing on a Xilinx Zynq ultrascale+ device.
no further requirements (i.e ECB mode is enough, without authentication as the rest is done in software).

Anyone who did it can recommend on a working and stable core ?

Thank you
Guy
ePiccolo Engineering

[rstofer]

OpenCores.org has one under Project -> Crypto.  I don't know anything about it.

[dolbeau]

I'm using the one from https://github.com/secworks/aes for AES128, planning to add/move to AES256 (core does both, encrypt & decrypt). I'm instantiating the aes_core not the high-level aes. Works for me...

[Guy Shemesh]

Thank you very much dolbeau for the recomendation,

I have used the Secworks and it's working great. Simple, working and easy to use. 

Guy

[dolbeau]

Thank you very much dolbeau for the recomendation,
I have used the Secworks and it's working great. Simple, working and easy to use. 

Excellent :-) BTW I since discovered an updated implementation of the same core - the 'aes-speed' from https://trac.cryptech.is/wiki/GitRepositories. It's larger but faster (cycles-wise), with the same interface. Depending on your requirements it might be an option.

They also have a bunch of FPGA-proven implementations for other algorithms.

[Guy Shemesh]

Wow!

Sorry only now I see this, it looks amazing!

Indeed the other AES took 72 cycles/block, now I see it's down to 20 cycles/block !

I had already finished my project for this so I could not test it. And regarding the relatively long encryption/decryption time, I hid it -:) We also have a software SHA256 which takes quite alot from the processor, so I let these processes work in parallel (PL-AES / SW-SHA).

Thanks dolbeau, I'll keep this link as I see there are many other interesting implementations there

Best Regards and keep safe
Guy