What the hell is up with Vitis HLS.

[Refrigerator]

Guys i can't, absolutely can't make Vitis HLS generate an IP that receives an array of integers one per clock cycle.
I've been at it for two weeks now and i'm at my wits end.
We had this lab work in uni where we had to make a cross correlator with Verilog on Vivado and then do the same with Vitis HLS and compare the two.
To those who don't know here's how Vitis HLS works: C++ -> ?? -> Verilog. 
I can write C++ and i can write Verilog just fine, but what i can't seem to do is read the mind of some stupid program that shoehorns my C++ into Verilog and how it does what it does.
Xilinx HLS guide is arguably more useless than ASF4 because they give examples that bring more confusion that anything. 

I'd show all of my failed code, but let's be honest, nobody wants to look through 1000 lines of code that doesn't work. 

The problem is that i need to generate the IP and test it on Vivado with Verilog and i can make my code work fine on Vitis, because it's C++, but once the IP is generated it's just broken.
So now i've reduced my efforts to just inputting an array and then outputting the same array but even that has proven to be impossible.

Code: [Select]

#define datsize 6


static volatile int counter;
static volatile int X_arr [datsize];

void IN_and_OUT(/*int* clicks,*/ int X_in[datsize], int X_out[datsize]) {

#pragma HLS interface mode=axis port=X_in,X_out
//#pragma HLS INLINE
//#pragma HLS DATAFLOW
for (unsigned i = 0; i < datsize; i++) {

//int temp = X_in[i];

//X_arr[i] = temp;
X_arr[i] = X_in[i];
}

for (unsigned i = 0; i < datsize; i++) {

X_out[i] = X_arr[i];
}

// for (unsigned i = 0; i < datsize; i++) {
//
// counter ++;
// *clicks = counter;
// }


}
Here's what i have so far that does almost-maybe-sorta-kinda but not really work. And it looks so simple to me, just two for loops, and according Xilinx guide this should mean that one array element is received per clock cycle, and that, unless #pragma HLS dataflow is specified, the two loops will work sequentially.
Well guess what - it doesn't. First for loop takes array elements but very slowly over multiple clock cycles, meanwhile the second for loop just fires full auto whatever it has.
Both for loops are essentially the same, yet work completely differently, they both run at the same time and once the first loop finishes, the second halts, even though it has been looping over and over again the entire time. 

I've been trying to basically reverse engineer HLS through this code because i can't seem to figure out how it works from the guides and github examples.

Feels like i've completely exhausted myself and whatever i do doesn't work. 

[bitslip]

Hey Refrigerator,

As painful as it maybe, see if you can get an older version of Vivado (2018, 2019) and try 'Vivado HLS'.  It can be run in standalone mode, taking in you C/C++ and outputting Verilog/VHDL RTL which you can inspect.

Take a look at this guide for help on some of the pragmas, unfortunately you have to litter your code ("decorate") with a lot of these to get Vivado HLS to work acceptably:

https://usermanual.wiki/Document/ug1270vivadohlsoptmethodologyguide.880892326.pdf

Ignore anything about OpenCL.