Hi everyone,
I want to embark on a project that wil conenct an FPGA to a device parallel bidirectional bus. The bus is not clearly documented, so I am not 100% sure when the device will output data on the bus. I want to protect both the FPGA dev board and the device because they cost some money.
I think resistors in series on every line is a good solution, but I don't know what value should I choose. The bus is 3.3V and its clock runs at up to 17MHz. Single data rate. I will have a ribbon cable (at least 20cm for ergonomics). So signal integrity is a factor, I think.
If I go with a value that limits the current below the FPGA's rating, say 3.3mA, the resistance is 1kohm. Empirically I think that's too high of an impedance considering the ribbon cable. If I go with something like 100ohm, empirically I think it can drive the ribbon cable but I don't know if the FPGA can survive that.
Is there a magical solution?