Renesas "lowest cost" ForgeFPGA low-density FPGA - free eval boards

[SiliconWizard]

At LCSC: https://www.lcsc.com/product-detail/Programmable-Logic-Device-CPLDs-FPGAs_Lattice-LCMXO2-1200HC-4TG144C_C1521637.html

I order a lot from them, so I'll probably just toss 10 or 20 of them into my next order of other parts.

Well, I ended up ordering about $300 of LCMXO2 in various sizes (100 and 144 pin packages), just to have parts in stock for projects.  That should keep me going for a year or so for "low cost" FPGAs until something better comes along.

In various sizes, do you mean only pin-wise, or also the number of LUTs? Because if you have bought only -1200 ones, that's cool but a bit limited. The MachXO2 comes with up to about 7000 LUTs (-7000 variant) and you can certainly fit much more logic in that, so for using these on various projects, I would have bought maybe a set of different variants, but maybe that's what you did.

[ataradov]

They seem to only have the lowest speed grade at this cheap price. And Lattice devices are not that fast to begin with. It is still fine for experiments, but many real projects will not do well at speed grade 4. And speed grade 6 devices cost the same as on Mouser.

Also, I just noticed "[NEW] View marketplace suppliers’ inventory" on LCSC. So they are also about to turn into crap aliexpress/wish clone.

[slburris]

In various sizes, do you mean only pin-wise, or also the number of LUTs? Because if you have bought only -1200 ones, that's cool but a bit limited. The MachXO2 comes with up to about 7000 LUTs (-7000 variant) and you can certainly fit much more logic in that, so for using these on various projects, I would have bought maybe a set of different variants, but maybe that's what you did.

Bought both pin and LUT variations in all nice leaded packages which are easy for me to solder.  Also have XC6SLX9 in LQFP-144 for the most LUTs.  And yeah, I know you can't directly compare LUT counts, different architectures, etc.  Beyond that, I'm out of hobby friendly soldering options.  Then I've used complete boards as "modules", from Digilent, random boards from Aliexpress (yes, I know), and ugh, reclaimed bitcoin miners. 

Who wouldn't want a board with a XC6SLX45 on it from a place called Grandmas Secret Closet?  https://www.ebay.com/itm/124648331917  I'm sure it's totally fine!

[glenenglish]

 So.. I am now seeing Renesas ForgeFlash FPGA eval kit  advertising in my EEVBLOG feed :-)

The  chip datasheet says VCCIO 1.7 to 2.75V

The eval kit says VCCIO 1.8 to 3.6

they cant both be right. 

I'll ask the question

[ataradov]

It is pretty clear that the kit was designed before the they knew that I/O ring is broken on the device. Then they decided to not fix the bug and declare it a feature.

[SiliconWizard]

Max VCCIO at 2.75V. Sales will be interesting.

[glenenglish]

I am going to get an eval board and apply 3.3V (you can) and measure impact on power consumption, and logic thresholds.
My bet is the static power on the HVIO banks goes up more than they want but surely that wouldnt stop them selling it as 3.3V

perhaps there is an issue with level shifting between IO cells and the core going bad.

Renesas sent me a reply to my question which just says "Has been actioned". But there's no changes to the documentation.... useless.
I'll ask the FAE.

[ftg]

Has anyone of you actually received the SLG7EVBFORGE ForgeFPGA devboard mentioned in the first post?
I sure have not.

[glenenglish]

Got a reply from Renesas

"There is an errata on this, and the new silicon works at 3.3V, there will be a datasheet update this quarter"
so, 3.3V yes.

[ataradov]

What an amateur hour. What errata? They rewrote the whole datasheet from the original version. It is not something you do by mistake.

[PCB.Wiz]

What an amateur hour. What errata? They rewrote the whole datasheet from the original version. It is not something you do by mistake.

'Yes, a novel way to release 'engineering samples' !  Maybe they ran so many, they wanted some design wins to use them up !

[bson]

OTP???  For developing bus timing, arbitration, control logic, clocks?

Is there a version with internal flash?

[ataradov]

It can be configured in a RAM-only mode for development over SPI interface. There is no flash version. Their whole story for this device is that they will mass program it for you OTP. The whole toolchain is oriented towards that.

And it can also act as a master and load the firmware from any SPI flash too.

[bson]

The board has an "emulation" mode.  The chip datasheet doesn't mention any emulation mode; it lists: external SPI flash, MCU, and OTP.  What is this emulation mode?  There is no schematic for the board in post 1, the documentation is literally just a single page quickstart.  Does this simply mean the board has an external SPI flash that's programmed in "emulation"?  They're not exactly using this word according to its meaning (physical impersonation).

I'm wondering what it takes to do development with this part; if it needs external SPI flash that's fine, as it can be left depopulated or removed later.  But I'd find internal flash far more practical for a CPLD.

[ataradov]

They don't position it as a CPLD. It is a direct continuation of a GreenPAK line, which always targeted OTP process.

No idea about emulation mode, I would assume this is just the SPI slave (MCU) mode where USB interface IC acts as a master.

Having SPI flash will take up I/O pins, which are already limited. In that sense, having a configuration master that can tri-state its pins after the configuration is done is a big plus.

[bson]

So they can load config from internal RAM, or load LUTs etc from SPI as if it were addressable RAM?  I don't see this mode listed in the datasheet...

[langwadt]

So they can load config from internal RAM, or load LUTs etc from SPI as if it were addressable RAM?  I don't see this mode listed in the datasheet...

datasheet points to this, https://www.renesas.com/us/en/document/mah/forgefpga-configuration-guide

[ataradov]

By RAM I meant the actual configuration RAM. There is nothing to load once it it loaded with the config. I don't know if it is actually RAM cells or something else, but the memory that in the final design gets loaded from the OTP memory.

That "RAM" can be loaded from SPI in passive or active mode.

It is loaded as a bit-stream, jut like any other FPGA would load, so it is not really addressable, you just push the bit-stream over SPI and it configures itself.