Dual Data Rate on Artix7 FPGA - PSRAM interface

[betocool]

Hey all,

This is a bit of a generic question. I'm considering a DDR 8bit PSRAM chip for a board design with an Artix7-50 FPGA. The datasheet for the chip (https://www.digikey.com.au/en/products/detail/infineon-technologies/S80KS5122GABHI020/15965288) for reference.

From the datasheet, the read operations occur at each rising and falling edge, the write operations are center aligned (Embarrasing, I don't seem to know how to attach images at the moment...)

Basically, I'd like to know if there are any good examples on how to use both clock edges on the Artix7 series, there doesn't seem to be native support for a DDR 8-bit PSRAM from the IP blocks.

Cheers,

Alberto

[glenenglish]

Use the ODDR and IDDR  primitives.
Use the VHDL Generate keyword to make a n bit wide  bus of primitives.
for clock, you could use a 4x  (quadrature) clock, or use a DCM/PLL etc to get a 90 deg phase shifted clock for data samping.

[betocool]

Thanks!

Just after I asked the question I found the ODDR and IDDR blocks, which will probably do what I need. I just ran a simulation and a proper example at a lower speed and it all seems to work well. I didn't know that I was looking for the ODDR / IDDR blocks.

Cheers,

Alberto