Ok, our problem here is the current Z80 code delivers you a read port pulse, simultaneously latching the read data on that exact pulse where it is obvious the data isn't yet ready.
What you want is not a delay due to interrupt, but a delivery of the read port port address when the command is received, which is actually already available on the first Z80 clock, and have the return data sampled before it is actually needed to be send to the z80 on clock position number 3. The wishbone interface appears to be way faster than the Z80, so this actually isn't a problem. We just need to capture the read data later at the right time. See your code on lines 486,487, and 494 which does the same as line 486.
However, we want to fix this properly and include the potential for a super fast Z80 in case we ever go to a Z80 FPGA core which can operate in the 100MHz region.
Step #1, take the above Z80 code and stuff it into my Z80 bridge interface Modelsim simulator and let's perform the Z80 code port read/write and see the waveform. Provide the new Z80 bridge simulator here so we can modify the code to make the bridge provide with a read in advance and then wait before line 487/488 are driven.
Helping you here will ensure in the future you know how to either use the Z80 bridge properly, or how to properly modify it to your liking.