Arrrg... Ok....
module GPU_DECA_DDR3_top #(
// **************** GPU controls.
parameter int GPU_MEM = 524288, // Defines total video RAM, including 1KB palette
parameter string ENDIAN = "Little", // Endian for 8bit addressing access.
parameter bit [3:0] PDI_LAYERS = 4, // Number of parallel window layers.
parameter bit [3:0] SDI_LAYERS = 4, // Number of sequential window layers.
parameter bit ENABLE_TILE_MODE [0:7] = '{1,0,0,0,0,0,0,0}, // Enable tile mode for each PDI_LAYER from 0 to 7.
// TILES are available to all SDI_LAYERS of an enabled PDI_LAYER.
// Each tile enabled PDI_LAYER will use it's own dedicated FPGA blockram.
parameter bit SKIP_TILE_DELAY = 0, // Skip horizontal compensation delay due to disabled tile mode features. Only necessary for multiple PDI_LAYERS with mixed tile enable options.
parameter bit ENABLE_PALETTE [0:7] = '{1,1,1,1,1,1,1,1}, // Enable a palette blockram for each PDI_LAYER from 0 to 7.
// Each palette enabled PDI_LAYER will use it's own dedicated FPGA blockram.
parameter bit SKIP_PALETTE_DELAY = 0, // Skip horizontal compensation delay due to disabled palette. Only necessary for multiple PDI_LAYERS with mixed palette enable options.
parameter int HWREG_BASE_ADDRESS = 32'h00000100, // The first address where the HW REG controls are located for window layer 0. The first 256 bytes are reserved for general purpose use.
// Each window uses 32 bytes for their controls, IE assuming 32 windows, we need 1024 bytes worth of address space.
parameter int HWREG_BASE_ADDR_LSWAP = 32'h000000F0, // The first address where the 16 byte control to swap the SDI & PDI layer order.
parameter int PAL_BASE_ADDR = 32'h00001000, // Assuming 32 layers where each palette is 1024 bytes, we will use 32768 bytes for the palette.
parameter int TILE_BYTES = 65536, // Number of bytes reserved for the TILE/FONT memory. We will use 64k, IE it is possible to make a 16x16x8bpp 256 character font.
parameter int TILE_BASE_ADDR = 32'h00004000, //
These lines:
parameter bit [3:0] PDI_LAYERS = 4, // Number of parallel window layers.
parameter bit [3:0] SDI_LAYERS = 4, // Number of sequential window layers.
parameter bit ENABLE_TILE_MODE [0:7] = '{1,0,0,0,0,0,0,0}, // Enable tile mode for each PDI_LAYER from 0 to 7.
Means that the tile mode will only function on layers 0,1,2,3.
These lines:
parameter int TILE_BYTES = 65536, // Number of bytes reserved for the TILE/FONT memory. We will use 64k, IE it is possible to make a 16x16x8bpp 256 character font.
parameter int TILE_BASE_ADDR = 32'h00004000, //
Means that when the Z80 or any other peripheral writes to memory address 32'h00004000 through 32'h00013FFF, you will be writing into the tile block memory memory address 20'h00000 through 20'h0FFFF.
This is hard wired and cannot be changed once compiled.
So, writing a font beginning at address 32'h00004000 means it's tile blockram address begins at 20'h00000.
Or, writing a font beginning at address 32'h00005000 means it's tile blockram address begins at 20'h01000.
Now, when setting the 16 bit register 'CMD_win_tile_base' address, it sets the first character '0' pointing into the 'tile blockram address', not DDR3 address. Remember, the value you set will be multiplied by 16 so that you may address more than 65536 bytes for the tile blockram memory. Now, since in the parameters you have a set limit of 65536 bytes, this means that setting a value above 4095, (65536/16-1), the tile memory blockram read address will loop around back to 0 as the line display buffer has no check for error addresses above the set parameter 'TILE_BYTES' size.
I hope this helps.