Ok, so far, so good.
Now for the reset values, the issue here is that the FPGA doesn't have 16kb of registers (that would be a 160k reg/gate fpga). What we are doing is selectively using reg at our convenience from that 16kb, not every one. This also means we do not and need not assign 16kb of reset values. The fewer resets we assign, the better. So, for the default/reset RESET_VALUES, we want the '1:RST_PARAM_SIZE' for the number of entries, and inside the reset values, we want to define the 14'hxxxx address and the 8'hxx data so that in your verilog if(reset), you perform a for loop from 1 to RST_PARAM_SIZE, and read in that loop read the 14'hxxxx address and assign the HW_REGS[14'hxxxx] <= 8'hxx.
This will allow you to selective indvidualy define reset values as specific points...
reset values will most likely look like:
parameter bit [23:0] RESET_VALUES[1:RST_PARAM_SIZE] = '{......
Where the contents will be 24'haaaadd, ....
[aaaa] being a 16 bit address and [dd] being 8 bit data.
Then in the for loop, you can select 14 of the upper 16 bits for the address pointer and use the lower 8 bits for the reset data. Or you can go straight to [31:0] and assign 16 bit data presets which will be easier since the majority of our presets will be 16bits long.
Inside the for loop, you should apply 8bits at a time and make an option to swap endian just in case.
Also, remember that in the main write data loop, the TAP_ data is 128bit with byte enables for the 16 bytes in the 128bit. Make a parameter on-top to select the bus TAP width of 128 bits and and the TAP address does go down to the 'byte', but the lower address bits are always equal to 0'. And when you store the data coming in, remember you wand an endian parameter option there too.
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