Note, I made your palette B&W to support the bitmap.
Ah, I had included a greyscale palette in the project (palette_greyscale.mif), but never mind.
I thought you were supposed to get 512k access from your Z80. The display is only 300kb. So you should be able to clear and draw on this display the slow way...
Yes that's true - the Z80 can access the bottom 512K as 16KB banks.
The Z80_Bus_Interface, however, controls what is read within that 512K. The
MEM_SIZE_BYTES parameter determines a hard limit beyond which the Z80 can't read the GPU RAM - this was to stop the Z80 reading beyond the top of the FPGA's block RAM. It's currently set to 98,304 bytes. Any reads beyond this value are ignored and the bridge will return 0xFF for addresses up to the last 16 bytes of the 512K. The last 16 bytes are the
BANK_ID section. Any reads
below that value should return valid DDR3 data. Obviously that isn't an issue now, so I need to look at that limit and either remove it entirely or disable it.
The three wires at lines 252-254 in
Z80_Bus_Interface.sv determine
where in the GPU RAM the Z80 is trying to read/write:
mem_in_bank is HIGH if the Z80 is addressing somewhere in the GPU's 512K window.
It should really be called mem_in_window.
mem_in_range is HIGH if the Z80 is addressing somewhere in the GPU's actual block RAM limits.
This can effectively be replaced with mem_in_bank above, as the DDR3 will always be larger than 512KB.mem_in_ID is HIGH if the Z80 is addressing the last 16 bytes of the 512KB window.
These last 16 bytes are the BANK_ID and allow the uCOM to identify that a GPU is available and show it's name/identifier.Make sure the Z80 works correctly with the ram.
Unfortunately there's no change in behaviour between this latest version and the previous one, aside from a static greyscale snow pattern on the screen.
If I dump a page from a 16KB bank, the initial values seem to be one higher than the bank number. i.e., if I dump the first page of (or any page within) bank 0x43, the initial values will all be 0x44. Bank 0x42 is all 0x43 values, etc. Only bank 0x40 is different (the first 16KB of GPU RAM) with 0x0F values, but probably because that could be the last value written to it as part of the screen setup in the DMI. It seems the last value written to any bank is the only value displayed in that bank thereafter.
When I get some time (maybe tomorrow), I'll try to get some Signal Tap traces of the read/write timings for you, unless you identify the issue before then.