Ok, here you go, the hopefully final Z80 interface with 'WAIT' processing.
The new simulator has 2 setups.
do setup_z80.do / run_z80.do
Will simulate the Z80 bus interface on it's own and will work with any FPGA vendor's version of ModelSim.
do setup_z80_to_DDR3.do / run_z80_to_DDR3.do
Will simulate the Z80 bus with my DDR3 ram controller, completely so you can see how the waits are effected.
This simulation requires Altera/Intel's version of ModelSim.
Things to read in the module parameter settings:
// Z80 bus timing settings.
.READ_PORT_CLK_POS ( 2 ), // Number of Z80_CLK cycles before the bus interface responds to a Read Port command.
.WRITE_PORT_CLK_POS ( 2 ), // Number of Z80_CLK cycles before the bus interface samples the Write Port command's data.
// 0 to 3, Number of CMD_CLK cycles to wait for DDR3 read before asserting the WAIT during a Read Memory cycle.
// Use 0 for an instant guaranteed 'WAIT' every read. (Safest for Read Instruction Opcode cycle.)
// Use 3 for compatibility with waiting for a BrianHG_DDR3 read cache hit before asserting the 'WAIT'.
.Z80_DELAY_WAIT_RI ( 0 ), // 0 to 4, Number of CMD_CLK cycles to wait for DDR3 read_ready before asserting the WAIT during a Read Instruction Opcode cycle.
.Z80_DELAY_WAIT_RM ( 3 ), // 0 to 4, Number of CMD_CLK cycles to wait for DDR3 read_ready before asserting the WAIT during a Read Memory cycle.
.Z80_WAIT_QUICK_OFF ( 1 ), // 0 (Default) = WAIT is turned off only during a low Z80_CLK. 1 = WAIT is turned off as soon as a read_ready is received.
and
// Read IO port addresses range.
.READ_PORT_BEGIN ( 240 ), // Sets the beginning port number which can be read.
.READ_PORT_END ( 249 ), // Sets the ending port number which can be read.
and new IO port when you are ready to get rid of the legacy IO port stuff inside the Z80 bus controller:
// ***********************************
// *** Z80 IO Read and Write ports ***
// ***********************************
output logic [255:0] WRITE_PORT_STROBE = 0 , // The bit [port_number] in this 256 bit bus will pulse when the Z80 writes to that port number.
output logic [7:0] WRITE_PORT_DATA [0:255] , // The array [port_number] will hold the last written data to that port number.
output logic [255:0] READ_PORT_STROBE = 0 , // The bit [port_number] in this 256 bit bus will pulse when the Z80 reads from that port number.
input wire [7:0] READ_PORT_DATA [0:255] , // The array [port_number] will be sent to the Z80 during a port read so long as the read port
// number is within parameter READ_PORT_BEGIN and READ_PORT_END.
This was 3 solid days of work, so you better appreciate it.
I need read and write snapshots. I hope everything works now.
If not, play with the Z80_WAIT_QUICK_OFF and/or make Z80_DELAY_WAIT_RM =0.
Home
Help
Search
Login
Register
