The corrupt snow is because the FPGA cannot reach the requested speed along certain critical paths.
Revert the clk_2x_phase and try slowing down the system:
// **************** System clock generation and operation.
parameter int CLK_KHZ_IN = 50000, // PLL source input clock frequency in KHz.
parameter int CLK_IN_MULT = 32, // Multiply factor to generate the DDR MTPS speed divided by 2.
parameter int CLK_IN_DIV = 4, // Divide factor. When CLK_KHZ_IN is 25000,50000,75000,100000,125000,150000, use 2,4,6,8,10,12.
parameter int DDR_TRICK_MTPS_CAP = 600, // 0=off, Set a false PLL DDR data rate for the compiler to allow FPGA overclocking. ***DO NOT USE.
Right at the top of the _top.sv, the _MULT = 32, will run the system at 400MHz instead of 500MHz.
Also, change the compiler optimization to my option 'B'.
If your monitor cannot run at 48Hz, try a _MULT = 34, . This should output a 50Hz video signal.
If this doesn't work, I'll show you how to do the 250MHz mode.