I did not say change the port vector size.
// ************************************************************************************************************************************
// **************** BrianHG_DDR3_COMMANDER configuration parameter settings.
parameter int PORT_R_TOTAL = 2, // Set the total number of DDR3 controller read ports, 1 to 16 max.
parameter int PORT_W_TOTAL = 2, // Set the total number of DDR3 controller write ports, 1 to 16 max.
parameter int PORT_VECTOR_SIZE = 16, // Sets the width of each port's VECTOR input and output.
I said change the data_width to 8 for the read and write on port 2.
// PORT_'feature' = '{array a,b,c,d,..} Sets the feature for each DDR3 ram controller interface port 0 to port 15.
parameter bit [8:0] PORT_R_DATA_WIDTH [0:15] = '{ 8, 8,128,128,128,128,128,128,128,128,128,128,128,128,128,128},
parameter bit [8:0] PORT_W_DATA_WIDTH [0:15] = '{ 8, 8,128,128,128,128,128,128,128,128,128,128,128,128,128,128},
// Use 8,16,32,64,128, or 256 bits, maximum = 'PORT_CACHE_BITS'
// As a precaution, this will prune/ignore unused data bits and write masks bits, however,
// all the data ports will still be 'PORT_CACHE_BITS' bits and the write masks will be 'PORT_CACHE_WMASK' bits.
// (a 'PORT_CACHE_BITS' bit wide data bus has 32 individual mask-able bytes (8 bit words))
// For ports sizes below 'PORT_CACHE_BITS', the data is stored and received in Big Endian.
And I said raise the priority of read and write port 2 to the max.
parameter bit [2:0] PORT_R_PRIORITY [0:15] = '{ 1, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},
parameter bit [2:0] PORT_W_PRIORITY [0:15] = '{ 2, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},
// Use 1 through 6 for normal operation. Use 7 for above refresh priority. Use 0 for bottom
// priority, only during free cycles once every other operation has been completed.
// Open row policy/smart row access only works between ports with identical
// priority. If a port with a higher priority receives a request, even if another
// port's request matches the current page, the higher priority port will take
// president and force the ram controller to leave the current page.
// *(Only use 7 for small occasional access bursts which must take president above
// all else, yet not consume memory access beyond the extended refresh requirements.)
These are the changes to make all the IO read and write port 2 into an 8 bit ram port compatible with the Z80 and make sure that the Z80 on port 2 has a top read priority above all else.
(*** Note that port 2 is really [ 1 ] while port 1 where the RS232 debugger is tied to is on [ 0 ] )
Don't forget to enable the write mask 'CMD_wmask' on port 2 so the Z80 actually achieves a write.
Also remember to remove all traces of your original RS232 debugger buried inside your GPU core.
And, just in case, these are all your DDR3 controller interface IO ports:
// ****************************************
// DDR3 Controller Interface Logic.
// ****************************************
logic CMD_R_busy [0:PORT_R_TOTAL-1]; // For each port, when high, the DDR3 controller will not accept an incoming command on that port.
logic CMD_W_busy [0:PORT_W_TOTAL-1]; // For each port, when high, the DDR3 controller will not accept an incoming command on that port.
logic CMD_write_req [0:PORT_W_TOTAL-1]; // Write request for each port.
logic [PORT_ADDR_SIZE-1:0] CMD_waddr [0:PORT_W_TOTAL-1]; // Address pointer for each write memory port.
logic [PORT_CACHE_BITS-1:0] CMD_wdata [0:PORT_W_TOTAL-1]; // During a 'CMD_write_req', this data will be written into the DDR3 at address 'CMD_addr'.
// Each port's 'PORT_DATA_WIDTH' setting will prune the unused write data bits.
logic [PORT_CACHE_BITS/8-1:0] CMD_wmask [0:PORT_W_TOTAL-1]; // Write mask for the individual bytes within the 256 bit data bus.
// When low, the associated byte will not be written.
// Each port's 'PORT_DATA_WIDTH' setting will prune the unused mask bits.
logic [PORT_ADDR_SIZE-1:0] CMD_raddr [0:PORT_R_TOTAL-1]; // Address pointer for each read memory port.
logic CMD_read_req [0:PORT_R_TOTAL-1]; // Performs a read request for each port.
logic [PORT_VECTOR_SIZE-1:0] CMD_read_vector_in [0:PORT_R_TOTAL-1]; // The contents of the 'CMD_read_vector_in' during a 'CMD_read_req' will be sent to the
// 'CMD_read_vector_out' in parallel with the 'CMD_read_data' during the 'CMD_read_ready' pulse.
logic CMD_read_ready [0:PORT_R_TOTAL-1]; // Goes high for 1 clock when the read command data is valid.
logic [PORT_CACHE_BITS-1:0] CMD_read_data [0:PORT_R_TOTAL-1]; // Valid read data when 'CMD_read_ready' is high.
logic [PORT_VECTOR_SIZE-1:0] CMD_read_vector_out [0:PORT_R_TOTAL-1]; // Returns the 'CMD_read_vector_in' which was sampled during the 'CMD_read_req' in parallel
// with the 'CMD_read_data'. This allows for multiple post reads where the output
// has a destination pointer.
logic [PORT_ADDR_SIZE-1:0] CMD_read_addr_out [0:PORT_R_TOTAL-1]; // A return of the address which was sent in with the read request.
logic CMD_R_priority_boost [0:PORT_R_TOTAL-1]; // Boosts the port's 'PORT_R_PRIORITY' parameter by a weight of 8 when set.
logic CMD_W_priority_boost [0:PORT_W_TOTAL-1]; // Boosts the port's 'PORT_W_PRIORITY' parameter by a weight of 8 when set.
Remember, all control inputs need to be wired to a control, or a 0 or 1.
Yes you need to pass some of the output from the Z80 bridge to the top of your GPU module to feed this new TOP where the DDR3 controller and new RS232 debugger exists.
Also, you may need to change where I wired the new RS232 debugger's RXD/TXD to your chosen IOs.
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