Oooops, the module you are using uses x10 on the PLL instead of x5. I don't think they are using Altera's SERDES. If not, it may not be possible to achieve the 742.5mbps as the code cant run that fast if they are using a software SERDES instead of a hardware one.
The code internally seems to support DDRIO mode, IE shift 2 bits per clock. You will need to read up on how to get it to work, or it might be automatic...