Just as an aside, I've got the attached project building now, but it appears to be using some sort of megafunction to set up the TMDS outputs and I cannot assign pins in the Pin Planner to get the project to work on my EasyFPGA board with the DVI Tester. The pins are already assigned and read only when I go to the Pin Planner.
I'm thinking I should just remove the OBUFDS elements entirely from hdmi.sv (lines 319-334) and just connect tmds_current[] to the output pins whilst inverting the _n pin signal, allowing me to assign pins in Pin Manager as usual. Hopefully. Seems OBUFDS uses the altera_gpio_lite megafunction, but I can't find it in the IP Catalog so I can't seem to find where it's assigning the IO pins to the TMDS signals.
I'm probably going to get a lot of flak for not just doing it from scratch, but I like the promise of being able to output an HDMI signal and include audio in the bit stream - that's a major benefit over straight DVI and is why I'm plugging away at this example project.
Ok,I attached the simulation test bench.
Warning, in file: audio_clock_regeneration_packet.sv
I had to comment out line 41 and replace it with line 42 since Quartus 9.1 could not handle the "
real' " in the formula. Later versions of Quartus can handle the term properly, so, you should comment back in line 41 and comment out line 42. The difference is a potential rounding error with huge numbers and dividers.
I also bypassed the IOBUFF module to make it transparently pass the data through.
When loading the project into Quartus Prime, you will need to first change the Cyclone to the one on your developer PCB. You will only output the 'P' pins unless we inverted the N&P polarity in the circuit. If we did so, only output the 'N' port pin. Do not output the N&P together. Right now, I wired only the 'P' channel to all 4 outputs.
Next, you will need to first do a 'Start - Analysis & Synthesis'. Then go into the 'Pin Planner' and set the ' I/O Standard ' to LVDS. You will notice that the TMDS pins have automatically doubled to versions with and extra {n} at the end. Now, drag the 'non {n}' versions of the pins onto the correct differential 'P' output on the FPGA. Also set the CLK to the right Input as well. (You will notice that the pin-planner will automatically position the {n} versions of the output port to the 'n' pair on the LVDS output.)
Next, go into the assignment editor and copy & paste the assigned TMDS output pins and in the duplicate group, change their assignment name from IO standard to 'Fast Output Registers' and set the value to 'On'. Save the changes then compile. (Only the original 'output pin' names need the 'Fast output registers.)
Note that my last 2 instructions (defining the output as an LVDS differential and Fast Output register) can be properly set and defined in the IOBUF, but that will take reading some documentation on your part and learning everything about specifying the output buffer.
With your 20MHz scope, you should see a 25.2MHz signal on the TMDS_Clk pin on both FPGA IOs, N&P, of your test circuit, though if will look like a sine wave since your scope is even slower than 25MHz. If it looks OK, then try plugging in an HDMI monitor.
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