But before that, before entering the DDR3 controller, he need to read it's documentation and see what features and configuration he will want to use. He also needs to decide whether to tie everything together to the existing GPU via block diagram, or go 100% HDL and drop the block diagram entry he has been using to date and write modules merging his existing HDL cores.
Tackling the easiest task first, I'd like to stick with the block diagram. It provides me with an easily understandable overview of how all the modules interlink that I just wouldn't have with some large, unwieldy block of HDL instantiating everything.
As for the DDR features/configuration, I've made a start on the datasheet.
So you want me to specify things like the burst length, burst type, CAS latency, operating mode, DLL RESET, write recovery and precharge power down mode?
Without having much of a clue about all these configuration options, I guess I'd need BL8 as we won't be interested in BC4 nibbles. Sequential burst type?
Write Recovery is set as the result of a calculation - WR (cycles) = roundup (tWR [ns]/tCK [ns]). Were we looking at 200MHz for the DDR clock? That's tCK of 5ns, but how do I find tWR?
That's probably it for me for the next few days - got a busy weekend and next week. ![Undecided :-\](https://www.eevblog.com/forum/Smileys/default/undecided.gif)
For now, select a 300MHz ram clock and select a matching ram chip. The megafunction will automatically enter all those fields for you. I know they only have the -125/-15E versions of the ram chip. This is ok as we are not clocking up to the 1GHz of the ram chip available at LCSC.
The additional features like on-die-termination should also be enabled as by default, they are not.
Also, 'enable hard memory interface' should be disabled.
Begin with this.
You will want to make a new project with your chosen FPGA, 256 ball, -C7.
You will need to add a PLL which takes in your reference 50MHz and outputs 300MHz.
Set IO pins on selected banks. (Avoid using bank 5A for ram.)
Also, under controller settings, we will use the 'byte enable' and create 2 ports, 1 read and 1 write.
Begin here.
We will then occupy the ram controller with temporary dummy controls an compile to see if we can extend the FMAX beyond 300/600MHz.