For the external DDR memory interface, the CV Handbook Vol I section 6 spells it out.
Table 6-5 tells you the where the DQs blocks exist.
All x8, 3 of them on the bottom.
We need 3, plus we will also use an x8 block as the HDMI transmitter lanes.
Maybe the bottom and 1 lower left or right side set to 1.5v will be enough for the ram & HDMI.
Figure 6-2 shows the DQS pins and DLL connections on our chosen CV IC.
Figure 6-8 shows the PHYCLK networks.
Table 6-16 shows the 'Hard Memory Controller Width for CV ', in the F256 pin device, it is not bonded to the IOs.
You need the U484 or F484 device, or, M383 device to get the 400MHz.
So, we are stuck with 303MHz, 606mtps without any sort of overclocking the fabric.
Or the compiler allows a higher speed without timing violations because our design is so simple.
Or we write our own and cheat a little to get the IO port's theoretical ~800Mhz DDR data IO rate, though, 400MHz logic to control the ram would need to be a simple sequencer.