Arrg, stop the board. I tried using those pins in Quartus and it says that the maximum for the selected IO is 640mbs. Fine for 480p, but not 720p. I think I've just selected the wrong IO standard in Quartus, but I need to make sure if you want to attempt 720p.
Ok, 'STTL-2 Class II' on those chosen IOs supports 740mb/sec, so we are ok...
In fact, we can even do it non-differential. If the NXP will take in a non-differential and output proper HDMI, then you only need 4 outputs to drive the HDMI saving another 4 IOs. However, you loose the common mode noise rejection between the FPGA and NXP IC. But, I guess it is the same for DDR3 data lines...
Otherwise, the board is fine.
Ok, it's annoying how Quartus hounds you when you use their LVDS megafunction when compiling, checking the clocks exactly and aborting if you exceed a single MHz. I'm having trouble getting 740MHz and true differential working with the exact chosen IO, however, the code is simple enough to compile in a CV chip and Quartus tells you if you will achieve the official frequency or not.
This is also good if we use Quartus' DDR3 memory compiler and choose the IO pins. It will tell us straight in the face if we will achieve the 400MHz/800mtps mark or not.