Yes I'd been thinking about putting a test PCB together to confirm that the solution works, I just didn't know if the unmatched, non-paired traces going through header pins on the dev board to a second PCB would create more problems. If I can get 480p out of the dev board, then I'd be totally happy getting rid of the VGA output on the new GPU card.
It'll delay the actual GPU card production by a few weeks/month, but I think it's worth it for my peace of mind and will give me some time to focus back on finishing the ellipse drawing function.
Just need to confirm that the dev board has the right IOs available for the job, though. Have attached the schematics for the dev board I'm using.
Look at FPGA pins -> Header P2 pins: (use 4 adjacent pairs for the HDMI digital data)
38p/39n -> 38/37
49p/50n -> 32/31
52p/53n -> 29/28
54p/55n -> 27/26
59p/60n -> 24/23
ARRRRGGGG, these IO also go to a SDRAM chip according to the schematic... Maybe cut the traces or remove the ram chip...You only need 4 of these pairs. They are all located on header 'P2'.
The other signals, I2C & HPD and output enable control & gain signals may be wired to any other IOs.
I would make a narrow PCB which sits on the P2 Header itself. Make sure you can make JLPCB's cheap 5$ for 5PCBs fit on that connector. It may need to be a bit narrower which is why I listed all the possible matched N/P pairs.
Also, make sure you have the ability to change the dev-board's 3.3v regulator for a 2.5v since we will use want to use that IO voltage on the Cyclone V. NXP's amplifier chip only requires a differential 300mv signal coming in to drive the full TMDS output. It has auto level, auto gain and a 4 level set-able high frequency/edge enhancement boost capability set by 2 input pins.
Your test PCB should have the 8 series caps like in the schematic, but, it should also have 4 parallel load resistors just before the caps as an extra termination option. Also, the HDMI TMDS outputs should have test points, even though garbled, at least your 25MHz scope should be able to see the TMDS pixel clock line which is also 25MHz.
All other IOs should be wired as shown in the NXP datasheet.
Note that CycloneV no longer has the lower/higher FMAX speed restrictions of some IO banks compared the CycloneIV, so, some of the n/p pairs we have chosen have a 500MHz limit unlike the higher 740MHz LVDS limit of every differential pair on the CycloneV, so our goal here is 250MHz 480p and audio. 720p is not expected to work here.
Check the actual layout of your dev board so you may choose the straightest traces. You may also swap the n&p as in the FPGA, the buffer would be driven with negative logic. The important thing here is that you are using the pairs.
Again, check JLPCB's maximum dimensions for that 5$ for 5pcb deal and check if you can make a PCB which will at least to pin 32 of header P2. Any extra space should just have a header going off the edge of the PCB and you should get a female dual inline header with gold plated pins to plug your test PCB onto the dev board.
Prep this PCB quick, then we can get onto doing the HDMI encoder and you also have the filled ellipse to finish in the geo unit.
Once confirmed, you can then edit the new CV GPU to your liking.