FPGA VGA Controller for 8-bit computer

[BrianHG]

Does that fill under the FPGA reach all the VCCDDR pins?
You can make the green more rectangle and cover all the IO pins under the FPGA as well.
Including making it a bit wider on the right of the ram to the regulator...

As for 6mil.  For a mid layer power-plane, 6mil is tight especially with so many vias all over the PCB, all that tight area.  Even if JLPCB can do 6mil trace/via clearance, for PCB manufacturing, when it comes to polygon fills, I like to at minimum add 2 mil, if not 4 mil to this figure allowing for some breathing room.

[nockieboy]

Does that fill under the FPGA reach all the VCCDDR pins?

It does, especially since I tightened the clearance, but it looks like I'll be widening that back to 10mil again after what you've said.  I had used a couple of traces to ensure the VCC_DDR pins were connected to the fill, despite the via clearances creating islands.

As for 6mil.  For a mid layer power-plane, 6mil is tight especially with so many vias all over the PCB, all that tight area.  Even if JLPCB can do 6mil trace/via clearance, for PCB manufacturing, when it comes to polygon fills, I like to at minimum add 2 mil, if not 4 mil to this figure allowing for some breathing room.

Okay, so too tight then.  Will return it to 10mil.

[asmi]

As for 6mil.  For a mid layer power-plane, 6mil is tight especially with so many vias all over the PCB, all that tight area.  Even if JLPCB can do 6mil trace/via clearance, for PCB manufacturing, when it comes to polygon fills, I like to at minimum add 2 mil, if not 4 mil to this figure allowing for some breathing room.

I've been doing 0.15 mm for a while for JLCPCB and they never had a problem with that. For WellPCB, which is more advanced fab that I use for 6 layer boards (as JLCPCB's 6 layer stackup sucks for high-speed designs), I've been using 0.1 mm clearance, and again had no problems whatsoever.
BTW - JLCPCB can do down to 3.5/3.5 mil trace/spacing. 6 mil traces is a stone age tech at this point.

[nockieboy]

As for 6mil.  For a mid layer power-plane, 6mil is tight especially with so many vias all over the PCB, all that tight area.  Even if JLPCB can do 6mil trace/via clearance, for PCB manufacturing, when it comes to polygon fills, I like to at minimum add 2 mil, if not 4 mil to this figure allowing for some breathing room.

I've been doing 0.15 mm for a while for JLCPCB and they never had a problem with that. For WellPCB, which is more advanced fab that I use for 6 layer boards (as JLCPCB's 6 layer stackup sucks for high-speed designs), I've been using 0.1 mm clearance, and again had to problems whatsoever.
BTW - JLCPCB can do down to 3.5/3.5 mil trace/spacing. 6 mil traces is a stone age tech at this point.

0.15mm makes life much easier as the fill will fully encircle any vias - saves me having to worry about adding 'floating' traces to connect isolated islands up to the main fill area.   

[BrianHG]

Does that fill under the FPGA reach all the VCCDDR pins?

It does, especially since I tightened the clearance, but it looks like I'll be widening that back to 10mil again after what you've said.  I had used a couple of traces to ensure the VCC_DDR pins were connected to the fill, despite the via clearances creating islands.

As for 6mil.  For a mid layer power-plane, 6mil is tight especially with so many vias all over the PCB, all that tight area.  Even if JLPCB can do 6mil trace/via clearance, for PCB manufacturing, when it comes to polygon fills, I like to at minimum add 2 mil, if not 4 mil to this figure allowing for some breathing room.

Okay, so too tight then.  Will return it to 10mil.

No copper/meat between vias, go back to 6mil...

[BrianHG]

As for 6mil.  For a mid layer power-plane, 6mil is tight especially with so many vias all over the PCB, all that tight area.  Even if JLPCB can do 6mil trace/via clearance, for PCB manufacturing, when it comes to polygon fills, I like to at minimum add 2 mil, if not 4 mil to this figure allowing for some breathing room.

I've been doing 0.15 mm for a while for JLCPCB and they never had a problem with that. For WellPCB, which is more advanced fab that I use for 6 layer boards (as JLCPCB's 6 layer stackup sucks for high-speed designs), I've been using 0.1 mm clearance, and again had to problems whatsoever.
BTW - JLCPCB can do down to 3.5/3.5 mil trace/spacing. 6 mil traces is a stone age tech at this point.

You haven't been using 2oz copper in the mid layers, JLPCB cant do 3.5 clearance on a mid layer with 2oz copper.
OK, so a number of my PCBs have power & RF power on them & I do use thicker copper for lower impedance power & it's heat dissipation advantages.

[asmi]

You haven't been using 2oz copper in the mid layers, JLPCB cant do 3.5 clearance on a mid layer with 2oz copper.

But this one isn't 2oz copper. Or is it?

OK, so a number of my PCBs have power & RF power on them & I do use thicker copper for lower impedance power & it's heat dissipation advantages.

I never had to use anything more than 1oz copper in any of my designs as I've been always trying to design the most efficient PDS I can, this has a nice side effect of lowering heat dissipation. That said, I had to use heatsinks for FPGAs as some of those dissipate too much power to safely sink it all into PCB.

Also - thicker copper does not lower plane impedance due to skin effect. Which is why most high-speed designs use 1/2 Oz power planes as this allows for finer geometry. It does affect current carrying ability, but unless we're talking about really high-end FPGA or CPU which consume 30+ Amps of current, typical power planelet is usually more than enough.

[BrianHG]

Also - thicker copper does not lower plane impedance due to skin effect.

The skin effect is at the high/RF frequency range component of your load, not the low the frequency & DC load component...

Yes, 1/2oz if fine for this project.

And 1oz for me has proven useful and on those layers, the 3.5mil is too tight to get good best possible yield over thousands of PCBs.

[nockieboy]

Yes, 1/2oz if fine for this project.

And 1oz for me has proven useful and on those layers, the 3.5mil is too tight to get good best possible yield over thousands of PCBs.

I'm using 1oz copper for this PCB - it's all I've ever used, to be honest.  I'm also hoping that the yield is sufficient for 5 PCBs, not so worried about thousands as I won't be mass-producing this design, I'm sure! 

[asmi]

The skin effect is at the high/RF frequency range component of your load, not the low the frequency & DC load component...

Exactly, reducing impedance at high frequency is the most important goal because decoupling caps are not very effective at these frequencies due to their own ESL and inductance of traces and vias. At lower frequencies decoupling caps work just fine.

[BrianHG]

Yes, 1/2oz if fine for this project.

And 1oz for me has proven useful and on those layers, the 3.5mil is too tight to get good best possible yield over thousands of PCBs.

I'm using 1oz copper for this PCB - it's all I've ever used, to be honest.  I'm also hoping that the yield is sufficient for 5 PCBs, not so worried about thousands as I won't be mass-producing this design, I'm sure! 

At low quantity, JLPCB does a flying probe test to ensure all your PCBs are perfectly fine.  Don't confuse my work where I'm shaving only a dollar or so for some large expensive PCBs which must also endure in the field where they regularly cycle between freezing and boiling temperatures on a regular basis.  The recommendations I make don't really apply to this PCB, but can still be considered cautious practice when such fine clearances of 3.5mil everywhere arent needed.

[mariush]

Reading the last 2-3 pages made me think ... have you thought if it wouldn't it be easier or cheaper to just put a sodimm ddr1 slot on the board? They're maybe a couple of dollars is small quantities and there's lots of 512MB - 1 GB sodimm sticks on eBay.
Only issue I see is sticks being 64 bit wide, but maybe you could wire only the bottom 24-32  bits and use a part of the sticks somehow?

[nockieboy]

Okay, I've swapped the IOs around for DDR_D0, DDR_D5, DDR#_CSn and DDR_RWDS to preferential, or in the case of the data lines - required - IOs on the FPGA.

Routing for the chip selects is a little roundabout - would appreciate thoughts on whether it's appropriate.  If it's not, though, then I'm lost as to how we're supposed to get DRAMs connected up to the FPGA.

The other issue is the highlighted green line in the image.  This is my preferred - and at the moment, only - method of routing the signal to its required IO pin.  Can I get away with passing a 5mil trace through an 0402 component?

If not, this whole DRAM is going to require more of a routing re-think on my behalf.

[BrianHG]

Okay, I've swapped the IOs around for DDR_D0, DDR_D5, DDR#_CSn and DDR_RWDS to preferential, or in the case of the data lines - required - IOs on the FPGA.

Routing for the chip selects is a little roundabout - would appreciate thoughts on whether it's appropriate.  If it's not, though, then I'm lost as to how we're supposed to get DRAMs connected up to the FPGA.

The other issue is the highlighted green line in the image.  This is my preferred - and at the moment, only - method of routing the signal to its required IO pin.  Can I get away with passing a 5mil trace through an 0402 component?

If not, this whole DRAM is going to require more of a routing re-think on my behalf.

I need to see the net labels.  However, the strategy I would use is cut all the blue traces off of the FPGA just to it's edge.  Only concern yourself with choosing the best D0..D7 signals.  Then route the RDWS and reset on the top layer if necessary or possible noting that you cannot touch the CLKn&p line.

Maybe a hires .pdf of the pcb will help.

I don't know about the spacing on the PCB, but, I might have personally rotated the rams 90 degrees just to make those clock lines look perfect straight.

[asmi]

Reading the last 2-3 pages made me think ... have you thought if it wouldn't it be easier or cheaper to just put a sodimm ddr1 slot on the board? They're maybe a couple of dollars is small quantities and there's lots of 512MB - 1 GB sodimm sticks on eBay.
Only issue I see is sticks being 64 bit wide, but maybe you could wire only the bottom 24-32  bits and use a part of the sticks somehow?

They are having hard time routing 13 tracks to the memory, and you're offering them to instead route 60+? That doesn't sounds like a sensible solution to me. If anything, I'd rather place a single x16 DDR3(L) module. It would give a ton of bandwidth with just about 50 pins, and would be easier to route than full SODIMM interface. But routing entire interface on a 4 layer board is not easy. Take a look at the project in my signature, there is 16bit DDR2 module routed on a 4 layer PCB, but the only reason I was able to do it was because the package pinout was designed very well for that kind of layout. On larger packages I wouldn't even think of doing this on a 4 layer PCB and would go straight to 6 layer one.

[asmi]

I don't know about the spacing on the PCB, but, I might have personally rotated the rams 90 degrees just to make those clock lines look perfect straight.

Clock lines needs to be the longest in a group, which is why I left a ton of space around it's path for future length matching.

[BrianHG]

Reading the last 2-3 pages made me think ... have you thought if it wouldn't it be easier or cheaper to just put a sodimm ddr1 slot on the board? They're maybe a couple of dollars is small quantities and there's lots of 512MB - 1 GB sodimm sticks on eBay.
Only issue I see is sticks being 64 bit wide, but maybe you could wire only the bottom 24-32  bits and use a part of the sticks somehow?

Nockieboy went for the cheap 17$ 256pin fpga, not a nice 484 pin one with enough IO for real ram + that Z80 interface & full external 24bit dac.  If so, I would have recommended 1 single 16bit wide DDR2/3 chip @ ~1$ with a guaranteed 500mtps, if not 600mtps running 3-4x circles in speed around this 13 wire hyperbus solution.

[BrianHG]

I don't know about the spacing on the PCB, but, I might have personally rotated the rams 90 degrees just to make those clock lines look perfect straight.

Clock lines needs to be the longest in a group, which is why I left a ton of space around it's path for future length matching.

When using the dedicated PLL outputs in my Cyclone designs, I've been setting the PLL to shift/delay it's output by ~ +/-0.2ns increments and calculating trace length.
If used, read DQS is a little more touchy.

[nockieboy]

Nockieboy went for the cheap 17$ 256pin fpga, not a nice 484 pin one with enough IO for real ram + that Z80 interface & full external 24bit dac.  If so, I would have recommended 1 single 16bit wide DDR2/3 chip @ ~1$ with a guaranteed 500mtps, if not 600mtps running 3-4x circles in speed around this 13 wire hyperbus solution.

Yup, I'm victim to my own lack of skill, knowledge and confidence - not just with FPGAs, but electronics in general.  There's no way I could justify blowing over $50 on an FBGA484 package when I've never soldered a BGA before.  QFP-144s gave me a headache, so forgive me if I'm a little reticent to jump into self-assembling a 6-layer PCB with a BGA484 FPGA.  Those kind of production costs don't sit well with what I'm doing being described as a 'hobby', either.  I'd need to start selling products to keep the boss happy. 

I'm still not sure whether I should try soldering the FBGA-256 package myself, or get JLCPCB to do it.  It'd probably work out a lot cheaper if I did it myself, but a lot riskier in terms of success...

Have routed the DRAMs to the FPGA now, but I'm sure there's going to be some feedback on some of those route lengths.  I blame whoever designed the IO pin locations on the FPGA package - they clearly weren't concerned about how we're supposed to connect stuff up to them.

Reading the last 2-3 pages made me think ... have you thought if it wouldn't it be easier or cheaper to just put a sodimm ddr1 slot on the board? They're maybe a couple of dollars is small quantities and there's lots of 512MB - 1 GB sodimm sticks on eBay.
Only issue I see is sticks being 64 bit wide, but maybe you could wire only the bottom 24-32  bits and use a part of the sticks somehow?

I came across an old DDR2 stick of RAM on a shelf when I was clearing it out the other day and the thought did occur to me as well.  Then I matched the stick up to the uCOM's PCBs and it won't fit - the PCB is too small to fit the stick, let alone the connector/receptacle it fits into.  I scrubbed the idea at that point, without even getting to any of the other considerations that BrianHG and asmi have already raised.  Otherwise was a good suggestion. 

[asmi]

Just in case anybody is curious, here is what layout for 16bit DDR2 module on a 4 layer PCB looks like.
And with that, let's go back to the task at hand

[BrianHG]

Nockieboy went for the cheap 17$ 256pin fpga, not a nice 484 pin one with enough IO for real ram + that Z80 interface & full external 24bit dac.  If so, I would have recommended 1 single 16bit wide DDR2/3 chip @ ~1$ with a guaranteed 500mtps, if not 600mtps running 3-4x circles in speed around this 13 wire hyperbus solution.

Yup, I'm victim to my own lack of skill, knowledge and confidence - not just with FPGAs, but electronics in general.  There's no way I could justify blowing over $50 on an FBGA484 package when I've never soldered a BGA before.  QFP-144s gave me a headache, so forgive me if I'm a little reticent to jump into self-assembling a 6-layer PCB with a BGA484 FPGA.  Those kind of production costs don't sit well with what I'm doing being described as a 'hobby', either.  I'd need to start selling products to keep the boss happy. 

Your doing fine as this is your second PCB.  Back in 1983, my first PCB was done with a sharpie marker, a hobby drill bit with hand drill and it had only a few transistors on it...

To use a DDR2 chip like this one @2$: https://www.digikey.com/en/products/detail/winbond-electronics/W9751G8NB-25/11656260 (And we can guarantee 250MHz/500mtps support as that ram chip can go up to 800mtps & by every metric, the access on this ram chip will run circles around the HyperRam.)

To access all 64 megabytes, you would need another 19 outputs that what you are currently using.

You can only do this if you get rid of the analog VGA dac and run the TFP410 in 12bit DDR mode.  This means you free up 12 IOs immediately and you already have another >8 free to complete the DDR2 ram chip interface.  Really push it and instead of the x8 ram chip, you can use the x16 version of the ram chip (same price and size) and double your ram bandwidth.

Use this guy for 128 megabytes: https://www.digikey.com/en/products/detail/issi-integrated-silicon-solution-inc/IS43DR81280C-25DBL/6202050
Question, how long would it take an 8MHz Z80 to fill 128 megabytes?
Without the aid of the accelerated geometry processor...

[asmi]

You can only do this if you get rid of the analog VGA dac and run the TFP410 in 12bit DDR mode.  This means you free up 12 IOs immediately and you already have another >8 free to complete the DDR2 ram chip interface.  Really push it and instead of the x8 ram chip, you can use the x16 version of the ram chip (same price and size) and double your ram bandwidth.

Why do you need that TFP410 at all? Didn't you said that FPGA can directly drive HDMI out up to like 720p (~750 Mbps per diff pair)? I'd say get rid of it - this will free up a ton of pins for other purposes.
Also if going DDR, I'd rather go all the way to DDR3 as they provide larger capacity for the same price over DDR2 - for like $5-6 you can get a 512 Mbytes device!

Question, how long would it take an 8MHz Z80 to fill 128 megabytes?
Without the aid of the accelerated geometry processor...

This is what DMA is for. Create a DMA with small memory-mapped aperture so that CPU can program data transfers, kick them off and let CPU do more useful things that shuffling bytes around.

[nockieboy]

Your doing fine as this is your second PCB.  Back in 1983, my first PCB was done with a sharpie marker, a hobby drill bit with hand drill and it had only a few transistors on it...

Thanks.   I just feel like I know nothing compared to you guys.

To use a DDR2 chip like this one @2$: https://www.digikey.com/en/products/detail/winbond-electronics/W9751G8NB-25/11656260 (And we can guarantee 250MHz/500mtps support as that ram chip can go up to 800mtps & by every metric, the access on this ram chip will run circles around the HyperRam.)

To access all 64 megabytes, you would need another 19 outputs that what you are currently using.

You can only do this if you get rid of the analog VGA dac and run the TFP410 in 12bit DDR mode.  This means you free up 12 IOs immediately and you already have another >8 free to complete the DDR2 ram chip interface.  Really push it and instead of the x8 ram chip, you can use the x16 version of the ram chip (same price and size) and double your ram bandwidth.

Use this guy for 128 megabytes: https://www.digikey.com/en/products/detail/issi-integrated-silicon-solution-inc/IS43DR81280C-25DBL/6202050

Right, well now we're getting into the big thing I wanted to discuss before I go much further with the PCB.  I can't remember why I opted for the TFP410 in the first place (and admittedly haven't bothered to go back to that part of the thread to find out), but if I can get a DVI-D interface up and running, I'll be dropping the VGA output like a stone.  If I can skip the TFP410 altogether and just drive an HDMI socket straight from the FPGA, then that would be the gold standard - it would free up more than 12 IOs... and presumably make the DDR2 chip a preferable alternative to the HyperRam chips.

I'd just need some persuading that the DVI output would work - but it's even simpler than the VGA output I've currently got, so I guess I'm happy to just go with that as an alternative to the TFP410 and ADV7125 mess I've currently got going on.

Question, how long would it take an 8MHz Z80 to fill 128 megabytes?
Without the aid of the accelerated geometry processor...

Probably a little longer than it would take me to work out the answer. 

[asmi]

Thanks.   I just feel like I know nothing compared to you guys.

That's OK. Don't feel bad about it. Nobody was born with this knowledge, so at some point we all were in your position. The important thing is your willingness to learn. If it's there, the rest is just a matter of time.

[FenTiger]

If I can skip the TFP410 altogether and just drive an HDMI socket straight from the FPGA,

Watch out for backpowering.

I have an FPGA board (Digilent Zybo Z7-20) with an HDMI output, and the manual says

The HDMI TX port does not include a buffer for improving signal integrity, but does include an HDMI multiplexer
configured as a simple switch. This device is used to prevent displays from back-powering the Zybo Z7, and
otherwise has no effect on functionality. The benefit this adds is to make it possible to power cycle the Zybo Z7
while a display is attached to HDMI TX, which was not possible on previous Digilent boards.

Maybe this won't be a problem for you but I'd suggest checking first to be sure you don't make the same mistake Digilent's engineers did!