FPGA VGA Controller for 8-bit computer

[asmi]

128Mbit chips are dual-die, they only support fixed double latency (no variable one-two latency like 64Mbit).
Also I don't think you can extract more performance from HyperRAM by interleaving as they already allow very long bursts, which will amortize initial access latency. The only reason to put multiple chips on a single data bus is to increase memory capacity. And in this case it will make more sense to just use 128Mbit device, as it makes all those connects internally and there is no need to route anything.
If you do want higher bandwidth, you will need to wire these chips in parallel to two separate data buses. In this case, you will probably want to work with fixed 2 latency mode, as it will allow you to run memory chips in lockstep. You will need to make sure these two data buses are not substantially different in length, otherwise you might have timing issues, especially if you don't use RDWS signal as read clock (a-la DQS), which is how it's meant to be used.

[asmi]

I had exactly the same problem when I viewed your changes.  I think part of the issue was having a selection filter on - when I turned it off, the response time improved dramatically.  I guess it doesn't help that it's an online tool and runs mostly in your browser, so it's not going to be as sharp and snappy as a dedicated desktop program.  The desktop version they provide for download is basically the EasyEDA web software running in a container as far as I can tell, so may not provide much performance improvement.

I decided to try desktop client, and it seemed a bit more reasonable as far as performance goes. As for selection filter - this is a tool that I use extensively in all eCADs as it makes me much more productive. Same goes for using colored nets - it makes routing easier as you clearly see which tracks need to go where.

Anyway, I've completed memory connections to the FPGA. I did some pin swapping, so please verify that this pinout will work. I tried to leave space for decoupling caps, but in my experience 0402 don't fit between 1 mm via grid, so you either will need to use 0201 (that is basically the only reason I use them), or get creative with placement to remove some vias and make room for decoupling caps. Once you complete placement, we will probably need to do a pass and match tracks length to minimize potential for timing issues. Since we're talking about 200 MHz DDR, bit time is 2.5 ns so even 10% tolerance is 250 ps, which is about 40 mm for outside tracks (signal speed is ~16.3 cm/ns). So we won't have to be very precise here, but still it's better to be conservative.

[BrianHG]

I tried to leave space for decoupling caps, but in my experience 0402 don't fit between 1 mm via grid, so you either will need to use 0201

This was the reason for the + channel and some space around the edges once you remove or change vias to adjacent unused ones.  Though, you will end up with fewer VCCint caps compared to what's in the schematic right under the FPGA, there should be a problem with this FPGA being the smallest one, or second one in the series.  After everything is done, I would still add 2-4 ceramic 10uf caps just outside the FPGA with 3-5 vias per pad to the GND & power plane to stiffen up the supply.

Interleaving 2 ram chips, meaning issue CMD for #1, then imediate CMD for #2, the reading or writing data from #1, then #2 means there is a empty command gap between each ram's previous and next command giving time for a blind refresh around read commands.  (need to double check this when running the ram at 200MHz...)

[nockieboy]

Anyway, I've completed memory connections to the FPGA. I did some pin swapping, so please verify that this pinout will work.

Thanks asmi.   Not sure about DDR_D0, though?  It's the only data line not connected to a DQ2R pin (I'm assuming DDR_D5 is fine connected to a DQS2R pin?)

After everything is done, I would still add 2-4 ceramic 10uf caps just outside the FPGA with 3-5 vias per pad to the GND & power plane to stiffen up the supply.

I'll add four 10uF caps into the schematic then. 

What about decoupling for the DRAMs?  1x100nF cap for each VCC_DDR pin?  I've added another 100nF cap into the schematic on the decoupling page as there's two VCC_DDR pins on the FPGA, looked like I was one cap down previously.  Do I need a larger cap for each DRAM as well?

[BrianHG]

Please move the VCCDDR on the top layer to the green layer.
You have space if you move the blue track horizontally and down a bit.
This also give you room to place the GND pad via next to the ram.

Move the RST to the bottom layer.

Now, you can place 1 decoupling cap above and 1 decoupling cap below each ram chip (top layer) going straight to the power pins with >25mil tracks.
You can also now place 1 decoupling caps on the left and right sides of each ram as well.

For the FPGA VCCDDR, you can place a 45 degree angle 0402 caps right under the FPGA between the VCCDDR and GND vias while the second one you have space to place it horizontally.  That's 8 caps at least, or preferably 10 decoupling caps for the VCCDDR.  I would also add a 10uf ceramic between the FPGA and ram.  (Another cap you don't have in your schematic.)

Everything else is perfect.

[asmi]

Thanks asmi.   Not sure about DDR_D0, though?  It's the only data line not connected to a DQ2R pin (I'm assuming DDR_D5 is fine connected to a DQS2R pin?)

I have no experience with CV, which is why I'm asking you guys to verify if that pinout would work or not.

What about decoupling for the DRAMs?  1x100nF cap for each VCC_DDR pin?  I've added another 100nF cap into the schematic on the decoupling page as there's two VCC_DDR pins on the FPGA, looked like I was one cap down previously.  Do I need a larger cap for each DRAM as well?

0.1 uF 0402 is my go-to decoupling cap, unless chip vendor tells something else.

[asmi]

Please move the VCCDDR on the top layer to the green layer.
You have space if you move the blue track horizontally and down a bit.
This also give you room to place the GND pad via next to the ram.

NO! Signal traces need an unbroken reference plane. This is high-speed design 101. Create a planelet on the power layer which would connect everything, and would also cover entire area under/above data traces. For high speed designs forget that power traces even exist. Because they suck as their inductance will kill whatever good regulation that comes out of DC-DC converter.

[BrianHG]

Please move the VCCDDR on the top layer to the green layer.
You have space if you move the blue track horizontally and down a bit.
This also give you room to place the GND pad via next to the ram.

NO! Signal traces need an unbroken reference plane. This is high-speed design 101. Create a planelet on the power layer which would connect everything, and would also cover entire area under/above data traces. For high speed designs forget that power traces even exist. Because they suck as their inductance will kill whatever good regulation that comes out of DC-DC converter.

I think you miss-read, did not ask you to break or even severely extend the blue tracks in any way.  Perhaps you just aren't seeing the cleaner path.

As for the VCCDDR, unless you have direct access to the VCCDDR on the top layer, it is already broken onto the green layer.  What I asked was to make an un-broken direct path to the RAM's VCC/GND pins to a decoupling cap on the top layer as an option and to get rid of the unusual loop you created which is worse than the dedicated power plane.  I thought you were going to do a rectangular flood fill for the VCCDDR when you were done encompassing the ram and the corner of the FPGA to gain that power-plane to GND plane capacitance and low impedance.  Note that what you see there is the only 1.8v components in the entire design.

As for any other power supply filtering, the PSP should be filtered at it's source (since we may not have control over it's distance to this logic section) while the logic/memory should also be filtered to a point where it appears to be a low frequency modulating (we cant help this) DC load.

[asmi]

As for the VCCDDR, unless you have direct access to the VCCDDR on the top layer, it is already broken onto the green layer.  What I asked was to make an un-broken direct path to the RAM's VCC/GND pins to a decoupling cap on the top layer as an option and to get rid of the unusual loop you created which is worse than the dedicated power plane.  I thought you were going to do a rectangular flood fill for the VCCDDR when you were done encompassing the ram and the corner of the FPGA to gain that power-plane to GND plane capacitance and low impedance.  Note that what you see there is the only 1.8v components in the entire design.

That wasn't me. I didn't touch VCCDDR net at all, aside from dropping few vias for it so that I can route around them.
Like I said above, the way to go is to create a solid planelet covering entire area where DDR traces go, as they need a reference plane in order to have 50 Ohm impedance (otherwise it's going to be much more than that). Same goes for another plane - it needs to be solid at least above/over entirely of DDR traces.

[BrianHG]

As for the VCCDDR, unless you have direct access to the VCCDDR on the top layer, it is already broken onto the green layer.  What I asked was to make an un-broken direct path to the RAM's VCC/GND pins to a decoupling cap on the top layer as an option and to get rid of the unusual loop you created which is worse than the dedicated power plane.  I thought you were going to do a rectangular flood fill for the VCCDDR when you were done encompassing the ram and the corner of the FPGA to gain that power-plane to GND plane capacitance and low impedance.  Note that what you see there is the only 1.8v components in the entire design.

That wasn't me. I didn't touch VCCDDR net at all, aside from dropping few vias for it so that I can route around them.
Like I said above, the way to go is to create a solid planelet covering entire area where DDR traces go, as they need a reference plane in order to have 50 Ohm impedance (otherwise it's going to be much more than that). Same goes for another plane - it needs to be solid at least above/over entirely of DDR traces.

Which is exactly what I was asking you to do....
I think we are just arguing about an incomplete photo where that VCCDDR net stood out as a mistake.

This is along the lines of what I was asking... Please excuse the paint software limitations.

[asmi]

Which is exactly what I was asking you to do....
I think we are just arguing about an incomplete photo where that VCCDDR net stood out as a mistake.

Yea probably.

This is along the lines of what I was asking... Please excuse the paint software limitations.

I left enough space for 0402 decoupling caps to be placed on the bottom right next to those pairs of Vcc/Gnd vias. See attached picture - light blue are pads for the caps on the bottom side (of course this is a Paint.NET art, real part footprints need to be placed there). These are spots for 4 caps, if you need more, you can move data traces a bit to create space for two more, or place those two on the top side of a board (and drop vias to the planes right next to them).

[BrianHG]

Ok, that's fine except for the bottom red VCCDDR going from 1 ram chip to the other  around for quite a distance for that single VCC pin.
That one is a NO-NO...

[asmi]

Ok, that's fine except for the bottom red VCCDDR going from 1 ram chip to the other  around for quite a distance for that single VCC pin.
That one is a NO-NO...

Yea. But that's what we are here for - to catch those typical novice's mistakes. I wasn't sure if you guys wanted more than 2 decoupling caps per device, which is why I only left space for two. But there is enough space on the bottom side to spread around DDR data traces to create enough room for two more decoupling caps and power vias. Hopefully I will have some time this evening to add these in.

[nockieboy]

Please move the VCCDDR on the top layer to the green layer.
You have space if you move the blue track horizontally and down a bit.
This also give you room to place the GND pad via next to the ram.

Move the RST to the bottom layer.

Now, you can place 1 decoupling cap above and 1 decoupling cap below each ram chip (top layer) going straight to the power pins with >25mil tracks.
You can also now place 1 decoupling caps on the left and right sides of each ram as well.

Have done the best I can, not sure I fully understood what you meant by moving the blue track horizontally and down a bit, but here's the latest:

For the FPGA VCCDDR, you can place a 45 degree angle 0402 caps right under the FPGA between the VCCDDR and GND vias while the second one you have space to place it horizontally.  That's 8 caps at least, or preferably 10 decoupling caps for the VCCDDR.  I would also add a 10uf ceramic between the FPGA and ram.  (Another cap you don't have in your schematic.)

Everything else is perfect.

Yes, asmi has done a good job there (thanks asmi!!!) Have yet to do this decoupling, aside from the top and bottom caps which you'll see in the previous closeup of the DRAMs.

I've also moved the AS and JTAG programming headers, seeing as I had some room between the three parts of the Z80 address buses to put the headers there and simplify routing.  That leaves me with some useful space at the top of the PCB - perhaps might have room for a USB connector and host chip.

Can we discuss the DVI-D output?  If I can get away with driving the HDMI connector directly from the FPGA, I'm all for doing that as it'll save me the headache of routing that rat's nest and I could do away with the TFP410.  Would appreciate thoughts on the idea, as it seems to be a worthwhile goal to strive for.  Even the HDL doesn't seem too hard for me to get my head around - in its basic form, at least.

Latest PCB design attached.  Note that I haven't reconnected VCCIO across the top from the reset button to the PCM5101 as I'm likely to be moving or getting rid of the reset button altogether.

EDIT: Ignore most of the above re: decoupling - I hadn't received notifications of new posts and wasn't aware of all that conversation since the post I was replying to here.  I'll take a closer look at the images and sort out the decoupling tomorrow (and the extra VCC_DDR trace down the bottom that needs removing).

[BrianHG]

The VCC and GND on high speed ICs should not have any length to the power plane if possible.
There should be a via as close as possible to each power pin going down to the power plane. Same for the decoupling caps right at those vias below the IC's power pins.

If you are using 0402 100nf caps, do it the right way under the ram and under the FPGA by the 2 adjacent power vias.

When I said an optional 10uf cap between FPGA and ram, this cap was an optional addition which should be by itself with the 3 vias on each side like you have going to the power planes, however, it should not be connected to any IC pins in this section.  Also, 1 additional 10uf cap could also be placed to the right of the second ram chip as well with the same no direct connect rule.

For high speed low voltage ICs, these rules should be kept.  Everywhere else, you are operating at such low frequency and such low current using regular 3.3v 74HC cmos, you do not need to be as strict, but once a rule is learned, keep on using it.

Also remember the FPGA VCCint 1.1v is also considered high frequency, high current, so, same decoupling caps rules apply.

Each matched length short trace between every power pin and via to a direct power plane ensures minimal inductive ring to each power pin and power plane as well as prevent some power pins receiving a differently tuned inductive ring on their power supply wreaking havoc within the IC's die and IOs.  Remember, many of the power pins also do merge at different points on the IC's DIE and if each one has a different frequency EMI noise, this adds current loops within the IC as well as generating such reflections on the IO and gates themselves.

[nockieboy]

DRAM update - have made changes based on previous feedback and included all the decoupling caps now.  It is especially tight for the VCC_DDR decoupling under the FPGA itself - would certainly appreciate a thumbs-up or thumbs-down on the current position of those two caps, though I'm not sure how/where else I can mount them.

Full PCB image included for context.


Closeup of DRAMs, showing decoupling cap placement and how I've moved the signal traces to accommodate them.  C128 and C129 are 0603 10uF.  I might take them up to 0805 just to give me some easy soldering to do... I know I'm pushing my limits when 0603 parts look huge. 


Another DRAM closeup, this time showing bottom traces more clearly.


I've removed the VCC_DDR power traces altogether and replaced them with a power plane on the PWR layer.  I can't upload the image for some reason. 

[BrianHG]

That looks a lot better.

Can I see the schematic.  The DDR_CS# seem excessively roundabout.
The only signal I don't care timing critical for is the DDR_reset.

[nockieboy]

Sure, here's the schematic.  I haven't touched the DDR pin assignments, but did raise a question regarding DDR_D0 a few posts back as it's connected to a non-DQ pin since asmi routed the DRAMs.  DDR_D5 is on a DQS pin too - not sure that'll make a difference?

[BrianHG]

Now that you know what the ram will look like, here is an example of tightening up the tracks on the bottom.
Not mandatory...

[BrianHG]

Sure, here's the schematic.  I haven't touched the DDR pin assignments, but did raise a question regarding DDR_D0 a few posts back as it's connected to a non-DQ pin since asmi routed the DRAMs.  DDR_D5 is on a DQS pin too - not sure that'll make a difference?

Errors...

DDR_D0 needs to be on DQ2R pin and preferably DDR_D5 as well.
DDR1_CSn & DDR2_CSn may be moved to pins F12, G12, E15, or H13  to free up 2 x DQ2R for D0 & D5.
DDR1_CSn & DDR2_CSn may also be routed on the top layer.

DDR_RWDS G13 and H13 may also be swapped.

DQ2R IO have a dedicated DFF input clock/clock enable wiring in the FPGA fabric from the DQS pins to the DQ2R input flipflops.  This allows the RAM to send a return clock it's data outputs on that DQ strobe matching the rise and fall times of the RAM's output drive.  Though, not mandatory to be used, to achieve the maximum ram clock frequencies and guarantee reading data without errors, especially above 200 MHz way into the GHz, this is the proper way to wire up DDR ram to the FPGA.  Think of the DQS pins when writing data, they become a dedicated clock/data enable output, when reading data, the switch into a dedicated clock/enable input hard wired direct to all the adjacent DQ pins so the ram chips will be sending the data clock back with the valid data.

[nockieboy]

Here's the trace tightening tweaks and (hopefully) the power plane image.

Errors...

DDR_D0 needs to be on DQ2R pin and preferably DDR_D5 as well.
DDR1_CSn & DDR2_CSn may be moved to pins F12, G12, E15, or H13  to free up 2 x DQ2R for D0 & D5.
DDR1_CSn & DDR2_CSn may also be routed on the top layer.

DDR_RWDS G13 and H13 may also be swapped.

No problem, will have a go at those later this afternoon.  Got one of those infamous Teams meetings coming up.     

[asmi]

Now that you know what the ram will look like, here is an example of tightening up the tracks on the bottom.
Not mandatory...

I did a loose layout on purpose to allow space for future length matching once we place and route everything else that needs to be in that part of a board.

[asmi]

Can I see the schematic.  The DDR_CS# seem excessively roundabout.

I would swap around DDR1_CSN and DDR2_CSN. You should be able to fit the latter between DDR1_CSN via and DDR_D2 trace. This should better balance the layout.

[BrianHG]

Here's the trace tightening tweaks and (hopefully) the power plane image.

Errors...

DDR_D0 needs to be on DQ2R pin and preferably DDR_D5 as well.
DDR1_CSn & DDR2_CSn may be moved to pins F12, G12, E15, or H13  to free up 2 x DQ2R for D0 & D5.
DDR1_CSn & DDR2_CSn may also be routed on the top layer.

DDR_RWDS G13 and H13 may also be swapped.

No problem, will have a go at those later this afternoon.  Got one of those infamous Teams meetings coming up.     

Arrrg, I hate fake polygon power planes.. You will need to shrink the clearance constraint for that layer so you get some copper filled meat around those adjacent vias...  Editing the outer diameter on all vias not connected on the power plane layers is a hassle, but this is usually done automatically on power planes in Protel/Altium which radically improves the power planes.  Don't worry, this PCB isn't at a level where you need to bother with this is a 10mil clearance will fill the power planes around those un-connected vias, though using the feature would double-triple the filled copper between the via drills when the unconnected via pad isn't there.

[nockieboy]

Arrrg, I hate fake polygon power planes.. You will need to shrink the clearance constraint for that layer so you get some copper filled meat around those adjacent vias...  Editing the outer diameter on all vias not connected on the power plane layers is a hassle, but this is usually done automatically on power planes in Protel/Altium which radically improves the power planes.  Don't worry, this PCB isn't at a level where you need to bother with this is a 10mil clearance will fill the power planes around those un-connected vias, though using the feature would double-triple the filled copper between the via drills when the unconnected via pad isn't there.

I've just reduced the clearance for the VCC_DDR area on the power plane, no issues.  Set it to 6mil, but having reviewed JLCPCB's capabilities, I'm not convinced it's valid as I can't find an 'area to via' minimum clearance specified.