Okay, it's been a busy couple of weeks for me and I've not had any time other than a couple of hours today to look at the schematic and your previous replies. I've done what I can. I've had to remove a lot of decoupling for the TFP410 because I don't think I'll have the room for it all, to be honest. I'm happy to give the setup a try without the reference design power supply isolation and decoupling, especially as it has been used the way I've done it (in fact, with even less decoupling) to good effect in other published designs.
I've re-jigged some of the FPGA connections to get the two DRAMs onto the board - hopefully I've done what you had in mind.
The schematic is updated but I haven't yet connected up the 1.8V power supply to the FPGA's IO bank for the DRAMs. I also haven't designed the variable-voltage output from the AMS-1117 (U19) for the DRAM yet. I'd be happy for some more info on that before I try - I guess I'll be using an SMD potentiometer in series with one of the resistors that sets the output voltage, but I'd probably be guessing at values at this stage without taking a closer look and spending some more time on that part of the schematic.
I've also updated the DAC to the suggested one and tucked its circuit up in the corner by the headphone socket to keep it out of the way as much as possible. Believe it or not, I know even less about analogue electronics than I do digital, so I've just gone with the reference schematic as close as possible from the datasheet. I've connected it up to Bank 2A.
My intention for the audio is to use an HDL synthesis of the classic AY-3-8910 PSG. At least initially. I guess having the flexibility to store samples and so on will just expand the possibilities.
It may be OK if you have functional HDL code already, however, I recommend reconstructing an advanced version of an Amiga Paula audio system. It is half as complicated as the geometry unit, but you can expect 8 channel sound, each channel with stereo, each with a volume and pitch table samples, all 16 or 8 bit.
I wouldn't have a clue where to begin with that and I'm mindful that I'm highly dependant on your help when your time is very restricted.
I do have an HDL version of the AY-8910 already that would work with my existing software in CP/M, so in theory it's just a case of adding an interface in the Z80_bridge and an interface from the 3-channel output of the HDL AY-8910 to the DAC. In
theory I should be able to manage that myself - so I'll give that a shot first before starting on something like the Paula chip.
Begin with the IO. To get the 500MTPS, you must use a top or bottom IO bank on the FPGA. It must have PLL output pins to feed the CLK & CLK# signals. It needs to be 1 IO bank since you need to change the VCCIO for that bank to 1.8v. I already looked at your current layout. You have 1 obvious choice and it will be an easy swapping of only a few IOs in your current design as soon as you clear up your schematic which seems to have a few unused additional labels.
Well, I've added the memory chips - not sure about the CLK & CLK# output pins - have picked pins marked 'p and 'n on the pin planner - so I'm hoping I've got that right.
For the regulator, you will add a small SMD trimpot tuned with an output range from 1.7v to 2.3v. If there are no errors during tests at 1.7v, then you know you can keep running it at 1.8v. I do not expect the entire 1.8v side to consume more than 80ma max when over-clocked. So, you may relax and feel safe with the same linear regulators you are currently using.
Excellent. Well, 1.8v power supply is in the schematic -
you won't see it on the PCB design as it's out of shot because I haven't placed it yet, I'm waiting to finish the variable output design first.
You have other minor errors in your schematic, but I'm waiting until you finish things up.
There's probably loads of errors - I do the best I can, but I really rely on everyone's help here to spot the obvious errors I sneak in to test you all.
1 thing, for the DAC's audio output DC filter caps, please change them to the 10uf non-polarized ceramic ones. Remember, part consolidation...
That was for the old DAC - the new one pumps out a proper AC signal so there's no need for DC filters, hence you won't find any polarised caps in the new design.