FPGA VGA Controller for 8-bit computer

[BrianHG]

Another very compact all integer midpoint ellipse on page 8 of this .pdf.

https://pdfs.semanticscholar.org/b3af/aff55ea9d5271e4d31abd4f0dd6e60be28d7.pdf

All we care about is the 'void ellipseMidpoint (int xCenter, int yCenter, int Rx, int Ry)'.
With region 1 & 2.

Still, no center ellipse with rotate.
Still looking...

[BrianHG]

All integer, axis aligned ellipse and general ellipse (angled)

Though the code is given in parts.
https://www.geometrictools.com/Documentation/IntegerBasedEllipseDrawing.pdf

It's basically showing you how to calculate the 8 zones in the arc.

[nockieboy]

I have been extremely busy the last couple of days, hence no activity here unfortunately, and my time is limited this weekend as well.  I got up hoping to make some progress on this today, but I'm getting nowhere and have spent my time staring at quadratic equations and code examples that I can't translate into FreeBasic for some reason or other.  Can you just clarify exactly what we're trying to achieve with the next step please?  I've got to write a Bezier curve function in FreeBasic that's easily translatable into HDL?

[BrianHG]

Ellipse or Bezier, your choice on how to attack the problem.

If you use the center aligned ellipse in the above papers, the easy one which has it in 2 simple for loops for the 2 half of the arc is one way to go.  However, you will have a separate ellipse/arc generator next to your line generator.  No problem doing this remembering that the above code would be modified to output sequences compatible with the pixel pipe and optional X filling engine.

Generating an integer Bezier means to create a circle or ellipse, your center 'pulling' point is the outer square box coordinates of the Bezier.  To make a straight line instead, that center point only needs to be on the begging or ending point of the line.  You are basically making 1 linegen algorithm which can perform the duties of line, ellipse (ie calling it 4 times, or since you have 2 of them, calling it 2x2 times), and the bonus of a bezier, or at least one where the sign of the arc cannot change.  However, this is a tricky thing to implement especially since I asked you to make it act as if it were part of the linegen.

Ok, what I have done is make the current linegen generate arcs by just adding 3 lines.
Now, the arcs do not close properly, but, you can see that the error is not tuning the arc & delta x/y properly, but you can see how simple it would be to add this to our existing verilog code is only the proper setup was used to make this work, as well as are direction.  Yes, there is a little more involved as a proper are generator supposed to flip the X&Y angle sign half way through as you have seen in the ellipse generators.

[nockieboy]

I would be more than happy with just a circle generator tbh, but am happy with a separate ellipse function that can do circles and ellipses.  My mind is melting with all this math - not that it's particularly deep in its original form, but that we're looking at highly optimised routines in a variety of source languages that make no sense to me.  That, or I'm just crap at this stuff and I need a holiday. 

I usually know when I'm lost in the software because I start to focus more on the hardware instead - have made some progress on the Cyclone 5 design recently as a result.

[nockieboy]

Okay, it's been a busy week and next it's just getting busier.  I don't have the time to sit and work out how to massage the Bezier code into something compatible with FreeBasic or HDL, so I'm going with the ellipse code:

Code: [Select]

Sub drawEllipse(ByVal x0 As Integer, ByVal y0 As Integer, ByVal x1 As Integer, ByVal y1 As Integer, ByVal colour as Integer, ByVal filled As Boolean = FALSE)
   Dim As Integer a = Abs(x1-x0), b = Abs(y1-y0), b1, x : Rem values of diameter
   Dim As Integer dx = 4*(1-a)*b*b, dy = 4*(b1+1)*a*a : Rem error increment
   Dim As Integer errd = dx + dy + b1 * a * a, e2 : Rem error of 1.step

   b1 = b And 1

   if (x0 > x1) then
       x0 = x1
       x1 = x1 + a : Rem if called with swapped points
   End If
   if (y0 > y1) Then
       y0 = y1 : Rem .. exchange them
   End If
   y0 = y0 + (b + 1) / 2
   y1 = y0 - b1 : Rem starting pixel
   a = a*(8*a)
   b1 = 8*b*b

   While (x0 <= x1)
      draw_pixel(x1, y0, colour) : Rem   I. Quadrant
      draw_pixel(x0, y0, colour) : Rem   II. Quadrant
      draw_pixel(x0, y1, colour) : Rem   III. Quadrant
      draw_pixel(x1, y1, colour) : Rem   IV. Quadrant
      If (filled) Then
        For x=x0 to x1
            draw_pixel (x, y0, colour)
            draw_pixel (x, y1, colour)
        Next x
      EndIf
      e2 = 2*errd
      If (e2 <= dy) Then
        y0 = y0 + 1
        y1 = y1 - 1
        dy = dy + a
        errd = errd + dy : rem  y Step
      End If
      If (e2 >= dx Or 2*errd > dy) Then
        x0 = x0 + 1
        x1 = x1 - 1
        dx = dx + b1
        errd = errd + dx : rem x Step
      End If
   Wend
 
   While (y0 - y1 < b)  : Rem too early stop of flat ellipses a=1
       draw_pixel(x0 - 1, y0, colour) : Rem -> finish tip of Ellipse
       y0 = y0 + 1
       draw_pixel(x1 + 1, y0, colour)
       draw_pixel(x0 - 1, y1, colour)
       y1 = y1 - 1
       draw_pixel(x1 + 1, y1, colour)
   Wend

End Sub

It works fine in FreeBasic, so if you have no objections I'll start translating this into Verilog as a separate function, though it's likely to take a while due to work.

I've also attached my first version of the schematic for the Cyclone V GPU card for comment if anyone is interested.

[Gribo]

Check page 27 of the TFP410 datasheet, you might not have enough decoupling capacitors.

[BrianHG]

Okay, it's been a busy week and next it's just getting busier.  I don't have the time to sit and work out how to massage the Bezier code into something compatible with FreeBasic or HDL, so I'm going with the ellipse code:

Code: [Select]

Sub drawEllipse(ByVal x0 As Integer, ByVal y0 As Integer, ByVal x1 As Integer, ByVal y1 As Integer, ByVal colour as Integer, ByVal filled As Boolean = FALSE)
   Dim As Integer a = Abs(x1-x0), b = Abs(y1-y0), b1, x : Rem values of diameter
   Dim As Integer dx = 4*(1-a)*b*b, dy = 4*(b1+1)*a*a : Rem error increment
   Dim As Integer errd = dx + dy + b1 * a * a, e2 : Rem error of 1.step

   b1 = b And 1

   if (x0 > x1) then
       x0 = x1
       x1 = x1 + a : Rem if called with swapped points
   End If
   if (y0 > y1) Then
       y0 = y1 : Rem .. exchange them
   End If
   y0 = y0 + (b + 1) / 2
   y1 = y0 - b1 : Rem starting pixel
   a = a*(8*a)
   b1 = 8*b*b

   While (x0 <= x1)
      draw_pixel(x1, y0, colour) : Rem   I. Quadrant
      draw_pixel(x0, y0, colour) : Rem   II. Quadrant
      draw_pixel(x0, y1, colour) : Rem   III. Quadrant
      draw_pixel(x1, y1, colour) : Rem   IV. Quadrant
      If (filled) Then
        For x=x0 to x1
            draw_pixel (x, y0, colour)
            draw_pixel (x, y1, colour)
        Next x
      EndIf
      e2 = 2*errd
      If (e2 <= dy) Then
        y0 = y0 + 1
        y1 = y1 - 1
        dy = dy + a
        errd = errd + dy : rem  y Step
      End If
      If (e2 >= dx Or 2*errd > dy) Then
        x0 = x0 + 1
        x1 = x1 - 1
        dx = dx + b1
        errd = errd + dx : rem x Step
      End If
   Wend
 
   While (y0 - y1 < b)  : Rem too early stop of flat ellipses a=1
       draw_pixel(x0 - 1, y0, colour) : Rem -> finish tip of Ellipse
       y0 = y0 + 1
       draw_pixel(x1 + 1, y0, colour)
       draw_pixel(x0 - 1, y1, colour)
       y1 = y1 - 1
       draw_pixel(x1 + 1, y1, colour)
   Wend

End Sub

It works fine in FreeBasic, so if you have no objections I'll start translating this into Verilog as a separate function, though it's likely to take a while due to work.

I've also attached my first version of the schematic for the Cyclone V GPU card for comment if anyone is interested.

Ok, for the verilog, what we will do here is use xy[0] for the X&Y center.  xy[1] for the width and height. x[2] for which quadrant to draw, 0 through 3 meaning draw only 1 quadrant per draw command.  For the fill enable, the command will only draw from the output arc x position to the x[0] center.

This way, you may draw ellipses and 90 degree arcs at 4 different corners to construct boxes with rounded corners.

[BrianHG]

I've also attached my first version of the schematic for the Cyclone V GPU card for comment if anyone is interested.

Change your audio dac to a PCM5101A.
https://www.ti.com/store/ti/en/p/product/?p=PCM5101APWR&HQS=OCB-tistore-invf-storeinv-invf-store-findchips-wwe

PCM5100A is also compatible, little lower quality, but, Farnell currently has stock of this one.

Use the dac supply with filter choke for the analog 3.3v & use optionally use vccio 3.3v for the digital.

[BrianHG]

If you get your PCB made by JLPCB, they will place the components for you if the parts are available at https://lcsc.com/ , the place where I found your Cyclone V for 18$.

Also, for your caps, use 10uf XR7 1206 or 1210 ceramic.  For 22uf, just use 2x10uf in parallel.
Do not use 0805 10uf ceramic.  Their capacitance really drops with voltage.

As for the DAC filter and boot caps, might as well use the same 10uf unless you do not want to consolidate parts.

[nockieboy]

Check page 27 of the TFP410 datasheet, you might not have enough decoupling capacitors.

Thanks Gribo - initially I added in loads of decoupling caps and was more careful about using different supply rails, but found I was running out of room very quickly on my board and I haven't even done the traces to the FPGA yet.  I've since found a working schematic and PCB design using the layout/decoupling setup I'm using here.  In fact, it uses less decoupling caps than I'm using.

[nockieboy]

I've also attached my first version of the schematic for the Cyclone V GPU card for comment if anyone is interested.

Change your audio dac to a PCM5101A.
https://www.ti.com/store/ti/en/p/product/?p=PCM5101APWR&HQS=OCB-tistore-invf-storeinv-invf-store-findchips-wwe

PCM5100A is also compatible, little lower quality, but, Farnell currently has stock of this one.

Use the dac supply with filter choke for the analog 3.3v & use optionally use vccio 3.3v for the digital.

The MAX5101 is in stock with Mouser (my preferred supplier if I'm not buying from China, which I won't be for this board) and it looks a lot simpler to use - it'll just require a small interface from the AY-3-891x HDL module to send the A/B/C channel data to the right register at the right time; something even I should be able to manage. 

What's the improvement using the PCM5101A?  I haven't got time to look tonight, but a quick glance at the datasheet indicates it uses I2S and doesn't look quite as straightforward as the MAX part?

[BrianHG]

What's the improvement using the PCM5101A?  I haven't got time to look tonight, but a quick glance at the datasheet indicates it uses I2S and doesn't look quite as straightforward as the MAX part?

I2S is a serial shift out protocol.  How hard is it to got from parallel to serial inside the FPGA?
The max part doesn't provide a 2 VRMS AC signal, IE output goes from -3v to +3v.  The PCM5101A has a built in negative voltage generator for it's internal output op-amps.
If you feed it a 48KHz audio, it has built in oversampling so you do not get aliasing on the audio output.
It's also 32bit per channel so you may have a software/firmware volume.
At 8 bit, the MAX part at low volume will have an undesirable broken bitstream sound to it.

[BrianHG]

Okay, it's been a busy week and next it's just getting busier.  I don't have the time to sit and work out how to massage the Bezier code into something compatible with FreeBasic or HDL, so I'm going with the ellipse code:

Code: [Select]

Sub drawEllipse(ByVal x0 As Integer, ByVal y0 As Integer, ByVal x1 As Integer, ByVal y1 As Integer, ByVal colour as Integer, ByVal filled As Boolean = FALSE)
   Dim As Integer a = Abs(x1-x0), b = Abs(y1-y0), b1, x : Rem values of diameter
   Dim As Integer dx = 4*(1-a)*b*b, dy = 4*(b1+1)*a*a : Rem error increment
   Dim As Integer errd = dx + dy + b1 * a * a, e2 : Rem error of 1.step

   b1 = b And 1

   if (x0 > x1) then
       x0 = x1
       x1 = x1 + a : Rem if called with swapped points
   End If
   if (y0 > y1) Then
       y0 = y1 : Rem .. exchange them
   End If
   y0 = y0 + (b + 1) / 2
   y1 = y0 - b1 : Rem starting pixel
   a = a*(8*a)
   b1 = 8*b*b

   While (x0 <= x1)
      draw_pixel(x1, y0, colour) : Rem   I. Quadrant
      draw_pixel(x0, y0, colour) : Rem   II. Quadrant
      draw_pixel(x0, y1, colour) : Rem   III. Quadrant
      draw_pixel(x1, y1, colour) : Rem   IV. Quadrant
      If (filled) Then
        For x=x0 to x1
            draw_pixel (x, y0, colour)
            draw_pixel (x, y1, colour)
        Next x
      EndIf
      e2 = 2*errd
      If (e2 <= dy) Then
        y0 = y0 + 1
        y1 = y1 - 1
        dy = dy + a
        errd = errd + dy : rem  y Step
      End If
      If (e2 >= dx Or 2*errd > dy) Then
        x0 = x0 + 1
        x1 = x1 - 1
        dx = dx + b1
        errd = errd + dx : rem x Step
      End If
   Wend
 
   While (y0 - y1 < b)  : Rem too early stop of flat ellipses a=1
       draw_pixel(x0 - 1, y0, colour) : Rem -> finish tip of Ellipse
       y0 = y0 + 1
       draw_pixel(x1 + 1, y0, colour)
       draw_pixel(x0 - 1, y1, colour)
       y1 = y1 - 1
       draw_pixel(x1 + 1, y1, colour)
   Wend

End Sub

It works fine in FreeBasic, so if you have no objections I'll start translating this into Verilog as a separate function, though it's likely to take a while due to work.

I've also attached my first version of the schematic for the Cyclone V GPU card for comment if anyone is interested.

You cheated!  That old code was already there and it is not a center ellipse, it is drawing an ellipse inside a box!

I'm curious as to why you didn't use this code:

Code: [Select]

*************Part1

int a2 = a*a , b2 = b*b , fa2 = 4*a2 ;
int x, y, sigma;

for ( x = 0, y = b, sigma = 2*b2+a2*(1-2*b) ; b2*x <= a2*y ; x++)
{
     DrawPixel ( xc+x , yc+y ) ;
     DrawPixel ( xc-x , yc+y ) ;
     DrawPixel ( xc+x , yc-y ) ;
     DrawPixel ( xc-x , yc-y ) ;

     if ( sigma >= 0 )
     {
          sigma += f a 2 *(1-y ) ;
          y--;
     }
     sigma += b2*(4*x+6);
}

*************Part2

int a2 = a*a , b2 = b*b , fb2 = 4*b2 ;
int x, y, sigma ;

for ( x = a, y = 0, sigma = 2*a2+b2*(1-2*a) ; a2*y <= b2*x ; y++)
{
     DrawPixel ( xc+x , yc+y ) ;
     DrawPixel ( xc-x , yc+y ) ;
     DrawPixel ( xc+x , yc-y ) ;
     DrawPixel ( xc-x , yc-y ) ;

     if ( sigma >= 0 )
     {
          sigma += fb2 *(1-x ) ;
          x--;
     }
     sigma += a2*(4*y+6);
}

From the document in my above post ' https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg3267128/#msg3267128 '.  It doesn't have that pesky flat ellipse issue.  And since it separates the are into 2-45degree segments, you can make my 90 degree bot corners into 45 degree edges if you like.

This is not important.  And for flat ellipses, ignore that portion when coding the verilog.  There is a better place within my code to bypass the ellipse all together and go straight to the draw line function.

[nockieboy]

Okay, it's been a busy week and next it's just getting busier.  I don't have the time to sit and work out how to massage the Bezier code into something compatible with FreeBasic or HDL, so I'm going with the ellipse code:

Code: [Select]

Sub drawEllipse(ByVal x0 As Integer, ByVal y0 As Integer, ByVal x1 As Integer, ByVal y1 As Integer, ByVal colour as Integer, ByVal filled As Boolean = FALSE)
   Dim As Integer a = Abs(x1-x0), b = Abs(y1-y0), b1, x : Rem values of diameter
   Dim As Integer dx = 4*(1-a)*b*b, dy = 4*(b1+1)*a*a : Rem error increment
   Dim As Integer errd = dx + dy + b1 * a * a, e2 : Rem error of 1.step

   b1 = b And 1

   if (x0 > x1) then
       x0 = x1
       x1 = x1 + a : Rem if called with swapped points
   End If
   if (y0 > y1) Then
       y0 = y1 : Rem .. exchange them
   End If
   y0 = y0 + (b + 1) / 2
   y1 = y0 - b1 : Rem starting pixel
   a = a*(8*a)
   b1 = 8*b*b

   While (x0 <= x1)
      draw_pixel(x1, y0, colour) : Rem   I. Quadrant
      draw_pixel(x0, y0, colour) : Rem   II. Quadrant
      draw_pixel(x0, y1, colour) : Rem   III. Quadrant
      draw_pixel(x1, y1, colour) : Rem   IV. Quadrant
      If (filled) Then
        For x=x0 to x1
            draw_pixel (x, y0, colour)
            draw_pixel (x, y1, colour)
        Next x
      EndIf
      e2 = 2*errd
      If (e2 <= dy) Then
        y0 = y0 + 1
        y1 = y1 - 1
        dy = dy + a
        errd = errd + dy : rem  y Step
      End If
      If (e2 >= dx Or 2*errd > dy) Then
        x0 = x0 + 1
        x1 = x1 - 1
        dx = dx + b1
        errd = errd + dx : rem x Step
      End If
   Wend
 
   While (y0 - y1 < b)  : Rem too early stop of flat ellipses a=1
       draw_pixel(x0 - 1, y0, colour) : Rem -> finish tip of Ellipse
       y0 = y0 + 1
       draw_pixel(x1 + 1, y0, colour)
       draw_pixel(x0 - 1, y1, colour)
       y1 = y1 - 1
       draw_pixel(x1 + 1, y1, colour)
   Wend

End Sub

It works fine in FreeBasic, so if you have no objections I'll start translating this into Verilog as a separate function, though it's likely to take a while due to work.

I've also attached my first version of the schematic for the Cyclone V GPU card for comment if anyone is interested.

You cheated!  That old code was already there and it is not a center ellipse, it is drawing an ellipse inside a box!

I'm curious as to why you didn't use this code:

Code: [Select]

*************Part1

int a2 = a*a , b2 = b*b , fa2 = 4*a2 ;
int x, y, sigma;

for ( x = 0, y = b, sigma = 2*b2+a2*(1-2*b) ; b2*x <= a2*y ; x++)
{
     DrawPixel ( xc+x , yc+y ) ;
     DrawPixel ( xc-x , yc+y ) ;
     DrawPixel ( xc+x , yc-y ) ;
     DrawPixel ( xc-x , yc-y ) ;

     if ( sigma >= 0 )
     {
          sigma += f a 2 *(1-y ) ;
          y--;
     }
     sigma += b2*(4*x+6);
}

*************Part2

int a2 = a*a , b2 = b*b , fb2 = 4*b2 ;
int x, y, sigma ;

for ( x = a, y = 0, sigma = 2*a2+b2*(1-2*a) ; a2*y <= b2*x ; y++)
{
     DrawPixel ( xc+x , yc+y ) ;
     DrawPixel ( xc-x , yc+y ) ;
     DrawPixel ( xc+x , yc-y ) ;
     DrawPixel ( xc-x , yc-y ) ;

     if ( sigma >= 0 )
     {
          sigma += fb2 *(1-x ) ;
          x--;
     }
     sigma += a2*(4*y+6);
}

From the document in my above post ' https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg3267128/#msg3267128 '.  It doesn't have that pesky flat ellipse issue.  And since it separates the are into 2-45degree segments, you can make my 90 degree bot corners into 45 degree edges if you like.

This is not important.  And for flat ellipses, ignore that portion when coding the verilog.  There is a better place within my code to bypass the ellipse all together and go straight to the draw line function.

   I wasn't passing the function off as my own work.  I did wonder why you hadn't mentioned using this code previously.  I took another look at all the Bezier stuff yesterday and being away from it for a week just made it (and the ellipse stuff) even less intelligible to me.

Then I remembered the code in the original geo.bas and wondered why we hadn't used that - it seemed to work fine so thought I'd use that?  Would be easy enough to tweak it to work from a centre point and radius, although I'd be fine with the current 'box' implementation.  Truth is, I haven't a flying clue what I'm supposed to be doing with this ellipse/Bezier stuff, I'm totally lost in it all.

It has given me an opportunity to make some headway on the hardware side, though.

[Gribo]

As much as I like being lazy, and copy stuff instead of actually doing it, the layout you posted will not pass a basic DFM review.
Have a look at the reference design, especially if you are going to try higher resolutions.

[nockieboy]

If you get your PCB made by JLPCB, they will place the components for you if the parts are available at https://lcsc.com/ , the place where I found your Cyclone V for 18$.

Yes, that's an option as I use JLCPCB for my boards.  I'm seriously considering it, even though it's expensive (e.g. I don't need five boards made up but that would be the minimum if I use their assembly process), but it would save me a LOT of headaches trying to solder BGA and QFN parts. 

Also, for your caps, use 10uf XR7 1206 or 1210 ceramic.  For 22uf, just use 2x10uf in parallel.
Do not use 0805 10uf ceramic.  Their capacitance really drops with voltage.

As for the DAC filter and boot caps, might as well use the same 10uf unless you do not want to consolidate parts.

Okie dokie, will use them - I take it these 1210 XR7 MLCC caps are fine and replacing polar caps with non-polar ones won't cause any issues?

The 10uF and 22uF caps on the Power sheet are 3216 tantalum capacitors - these are the same as what I've used on the current GPU board.

[BrianHG]

Okie dokie, will use them - I take it these 1210 XR7 MLCC caps are fine and replacing polar caps with non-polar ones won't cause any issues?

Those are fine everywhere.
But just don't take it that the Cyclone V is cheaper at LCSC, so is everything else.  Take a look at the cap price there:

https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_Samsung-Electro-Mechanics-CL31B106KQHNNNE_C318761.html
https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_Samsung-Electro-Mechanics-CL31B106MOHNNNE_C730480.html

You are throwing out 8x the money...
Or 4x for the 1210s:
https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_SAMSUNG_CL32B106KAJNNNE_10uF-106-10-25V_C39232.html

Same goes for almost every part on your PCB.

[nockieboy]

But just don't take it that the Cyclone V is cheaper at LCSC, so is everything else.  Take a look at the cap price there:

https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_Samsung-Electro-Mechanics-CL31B106KQHNNNE_C318761.html
https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_Samsung-Electro-Mechanics-CL31B106MOHNNNE_C730480.html

You are throwing out 8x the money...
Or 4x for the 1210s:
https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_SAMSUNG_CL32B106KAJNNNE_10uF-106-10-25V_C39232.html

Same goes for almost every part on your PCB.

Oh yes, I've spotted that already - must admit, I was a bit surprised that LCSC are cheapest (currently) for the Cyclone V.

As far as SMD assembly of the board goes, I'd only be buying and having the Cyclone V and power chips (QFN parts) assembled on the board, the rest I'd do myself.  Might consider the ADV7125 as part of the assembly too just to save me the hassle - seems they don't do the TFP410, though.

[BrianHG]

If you get your PCB made by JLPCB, they will place the components for you if the parts are available at https://lcsc.com/ , the place where I found your Cyclone V for 18$.

Yes, that's an option as I use JLCPCB for my boards.  I'm seriously considering it, even though it's expensive (e.g. I don't need five boards made up but that would be the minimum if I use their assembly process), but it would save me a LOT of headaches trying to solder BGA and QFN parts. 

Also, for your caps, use 10uf XR7 1206 or 1210 ceramic.  For 22uf, just use 2x10uf in parallel.
Do not use 0805 10uf ceramic.  Their capacitance really drops with voltage.

As for the DAC filter and boot caps, might as well use the same 10uf unless you do not want to consolidate parts.

Okie dokie, will use them - I take it these 1210 XR7 MLCC caps are fine and replacing polar caps with non-polar ones won't cause any issues?

The 10uF and 22uF caps on the Power sheet are 3216 tantalum capacitors - these are the same as what I've used on the current GPU board.

Are your IO optimized based on IO Bank and pin location for routing?
Or, will you do pin-swapping during layout?

[nockieboy]

As much as I like being lazy, and copy stuff instead of actually doing it, the layout you posted will not pass a basic DFM review.
Have a look at the reference design, especially if you are going to try higher resolutions.

I had a go at the reference design initially, but I was using the wrong chokes/inductors and they were taking up far too much room on the PCB, so I was keen to use a design that took up less space.  I've gone back to the reference design, but updated inductors.

[nockieboy]

Are your IO optimized based on IO Bank and pin location for routing?
Or, will you do pin-swapping during layout?

I've tried to keep within banks, but as you can see from the schematics I've not been able to keep all functions to the same bank.  A lot of this is because of prioritising pin placement, but I've never routed a BGA package before and fully expect to do some pin-swapping once you see the PCB layout and I learn a little about how I'm going to connect all these BGA pads up.

At the speeds we're working with (i.e. 8 MHz address/data buses and pixel clock speeds for the video out) and the fact all banks are running at the same 3.3V, how much effort should I be putting into fitting functions into the same bank?

Oh, I've also been unable to fit a DRAM into the BGA-256 version of the Cyclone V.  It only has 128 IOs, which is a step up from the Cyclone IV QFP-144 I'm currently using, but not enough to add in a DRAM.  Perhaps a larger BGA package should be considered, but the PCB is getting cramped...

The attachment shows where I am with the PCB layout currently.  Note that it doesn't reflect the changes made to the audio DAC and TFP410 decoupling, and doesn't have the decoupling caps for the FPGA placed yet.

I've yet to work out how many layers the PCB will need - I'm guessing it's going to have to be 4 layers - but I'm not sure which layers will be which, so I've just connected up power, bus lines and outer traces, working my way inwards using just the top layer so far.

[Gribo]

 
That's a nice looking board.

[BrianHG]

A single DDR2 dram will use 43 IOs, half will need to be in the top or bottom IO banks.
A single Hyperbus PSRAM will use 13 IOs, all in the top or bottom IO banks.  You will want 2 which means 26-2 = 24 IOs.
A single or dual ZBT Sync SRam will use 40 IOs, all in the top or bottom IO banks.

Choose your poison.

[nockieboy]

A single DDR2 dram will use 43 IOs, half will need to be in the top or bottom IO banks.
A single Hyperbus PSRAM will use 13 IOs, all in the top or bottom IO banks.  You will want 2 which means 26-2 = 24 IOs.
A single or dual ZBT Sync SRam will use 40 IOs, all in the top or bottom IO banks.

Choose your poison.

Ah okay... well, I can scrape together 24 IOs across three banks, but I'm going to need to re-jig the top banks if I'm going to use a PSRAM.  The FPGA is rotated 90 degrees CW on the PCB.