Fixing the 'Data_mux' module bug.
If you remember, in the Z80_bridge, we had to make the read requests and write requests going into the data_mux 2 clock cycles fat before we could solve the Z80 R&W errors.
See here:
https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg2859700/#msg2859700Anyways, the problem had to be solved 'properly' for the geometry pixel writer.
Step 1, simulate the original 'data_mux' with single clock cycle pulsed read and write requests from both ports A&B.
The green boxes and lines denote a read or write request, and the successful results.
The red boxes and lines denote a read or write request, but failure to execute a proper response.
Next, the re-write. The new 'data_mux_v2' with the same simulation stimulus:
As you can see, all the same read & write requests properly execute the desired proper response. In fact, as an improvement, right at 230ns, I placed 2 consecutive read requests simultaneously on on both port inputs for a total of 4 consecutive reads. The new data_mux_v2 now cached the 4 reads, interleaves the read addresses to the GPU ram and returns all 4 addressed data results to the correct port.
(You can sort of see why we had problems earlier. And also how adding another port for the geometry pixel writer would have been a nightmare if I didn't patch this one up properly...)
Attached are the Quartus Simulation test benches for both the original and the new data_mux 2:1 ram port emulator.
@nockieboy, step 1, change the data_mux to the data_mux_v2 in your GPU project from my working simulat source code. You will also need to add my 'fifo_3word_0_latency.sv' source code located in the simulation project to your GPU project as well.
Step 2, text the Z80 and RS232 interface.
If working, then go to step #3, change the Z80_bridge back the it's original intended mode of operation.
Step3, fix these lines in 'Z80_bridge.sv' so that the gpu_rd_req&wr_ena pulses are now 1 clock cycle wide like so:
// GPU RAM FLAGS
gpu_wr_ena <= Write_GPU_RAM && ~last_Z80_WR; // (data_mux bug fixed, pulse for only 1 clock, not 2) 2 ; // Pulse the GPU ram's write enable only once after the Z80 write cycle has completed
gpu_rd_req <= Read_GPU_RAM && ~last_Z80_RD; // (data_mux bug fixed, pulse for only 1 clock, not 2) 2 ; // Pulse the read request only once at the beginning of a read cycle.
And test the Z80 access + RS232 Debugger access. Report results please.